Patents by Inventor Yelehanka Ramachandamurthy Pradeep

Yelehanka Ramachandamurthy Pradeep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to form gate oxides of different thicknesses on a silicon substrate
    Patent number: 6235591
    Abstract: A method of fabricating gate oxides of different thicknesses has been achieved. Active area isolations are provided in a silicon substrate to define low voltage sections and high voltage sections in the silicon substrate. A sacrificial oxide layer is formed overlying the silicon substrate. A silicon nitride layer is deposited overlying the sacrificial oxide layer. A masking oxide layer is deposited overlying the silicon nitride layer. The masking oxide layer is patterned to form a hard mask overlying the low voltage sections. The silicon nitride layer is etched through where exposed by the hard mask thereby exposing the sacrificial oxide layer overlying the high voltage section. The exposed sacrificial oxide layer and the hard mask are etched away. A thick gate oxide layer is grown overlying the silicon substrate in the high voltage section. The silicon nitride layer is etched away. The sacrificial oxide layer overlying the low voltage section is etched away.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: May 22, 2001
    Assignee: Chartered Semiconductor Manufacturing Company
    Inventors: Narayanan Balasubramanian, Yelehanka Ramachandamurthy Pradeep, Jia Zhen Zheng, Alan Cuthbertson