Abstract: Vertically superimposed lateral gate-all-around metal-oxide-semiconductor field-effect transistors are provided, a structure of a novel three-dimensional integrated circuit such as a CMOS logic circuit that is composed of the vertically superimposed lateral gate-all-around transistors, a random-access memory and the like, and a manufacturing method for the novel three-dimensional integrated circuit are provided. The manufacturing method for the vertically superimposed lateral gate-all-around transistors includes: first preparing a monolayer channel and a source/drain, then protected with a sacrificial layer; preparing an insulating isolation layer, preparing above repeated structures on the insulating isolation layer; preparing an insulating spacer layer between the source/drain and a gate of each of the layers, a gate oxide, a gate, and a source/drain electrode in a unified manner, and finally preparing a connecting wire connected to the outside.

Abstract: Provided are a magnetic random access memory device and a manufacturing method therefor. The device comprises magnetic thin film structure bodies, and an electrode arranged around side surfaces of the magnetic thin film structure body. The method is: preparing a bottom electrode, preparing a magnetic thin film structure body on the bottom electrode; preparing a non-magnetic thin film structure body on the magnetic thin film structure body, and preparing another magnetic thin film structure body on the non-magnetic thin film structure body; etching the two magnetic thin film structure bodies and the non-magnetic thin film structure body to form a MTJ device, preparing an insulating layer thin film on the outer surface of the device, and preparing a VCMA electrode on the periphery of the side face of the magnetic thin film structure body requiring voltage application; and preparing a wire connecting the VCMA electrode to outside.

Abstract: A method of preparing the electronic material called silicon intercalated epitaxial monolayer graphene comprises the steps of growing large scale high-quality graphene on metal surface, depositing silicon on the prepared epitaxial graphene and annealing to high temperature to intercalate the silicon to the interface of graphene and metal surface. Depending on the quantity of the silicon deposited on the graphene surface, the numbers of the silicon layers on the interface can be controlled and adjusted.