Abstract: A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.

Abstract: The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.

Abstract: Provided is an herbal composition including an extract from an herbal raw material including at least one of Artemisia argyi, Ohwia caudata, Anisomeles indica (L.) O. Ktze, Ophiopogon japonicus, Houttuynia cordata, Platycodon grandiflorus, Glycyrrhiza uralensis, Perilla frutescens, and chrysanthemum. Also provided is a method for preparing the herbal composition and a method for preventing or treating a viral infection by administering an effective amount of the herbal composition to a subject in need thereof.

Abstract: Methods for preparing a void-free protective coating are disclosed herein. The void-free protective coating is used on a dielectric window having a central hole, which is used in a plasma treatment tool. A first protective coating layer is applied to the window, leaving an uncoated annular retreat area around the central hole. The first protective coating layer is polished to produce a flat surface and fill in any voids on the window. A second protective coating layer is then applied upon the flat surface of the first protective coating layer to obtain the void-free coating. This increases process uptime and service lifetime of the dielectric window and the plasma treatment tool.

Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.

Abstract: Methods for preparing a void-free protective coating are disclosed herein. The void-free protective coating is used on a dielectric window having a central hole, which is used in a plasma treatment tool. A first protective coating layer is applied to the window, leaving an uncoated annular retreat area around the central hole. The first protective coating layer is polished to produce a flat surface and fill in any voids on the window. A second protective coating layer is then applied upon the flat surface of the first protective coating layer to obtain the void-free coating. This increases process uptime and service lifetime of the dielectric window and the plasma treatment tool.

Abstract: A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.

Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.

Abstract: A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.

Abstract: A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.

Abstract: Methods for preparing a void-free protective coating are disclosed herein. The void-free protective coating is used on a dielectric window having a central hole, which is used in a plasma treatment tool. A first protective coating layer is applied to the window, leaving an uncoated annular retreat area around the central hole. The first protective coating layer is polished to produce a flat surface and fill in any voids on the window. A second protective coating layer is then applied upon the flat surface of the first protective coating layer to obtain the void-free coating. This increases process uptime and service lifetime of the dielectric window and the plasma treatment tool.

Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.

Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

Abstract: A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.

Abstract: A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.

Abstract: A vacuum plastic molding machine includes a heating device, a plurality of upright posts, a carrier assembly, and a demolding mechanism. The carrier assembly includes an upper carrier and a lower carrier. The upper carrier includes an upper frame, multiple upper movement structures, at least one rotation plate, at least one driving member, and at least one linking mechanism. An adjusting space is defined between the at least one rotation plate and the at least one linking mechanism. The lower carrier includes a lower frame, multiple lower movement structures, and at least one locking tenon. The locking tenon is placed into the adjusting space. The at least one driving member is rotated to change the position of the at least one locking tenon in the adjusting space, and to adjust the distance between the upper carrier and the lower carrier.

Abstract: A linkage brick assembly, comprising: a least one first linkage brick, at least one second linkage brick and at least one third linkage brick, each linkage brick comprising a top face, a bottom face and four side faces between the top face and the bottom face. Each of the side faces of the first linkage brick forms a traverse engaging groove extending laterally. Each of two opposite side faces of the four side faces of the second linkage brick forms a traverse engaging protrusion extending laterally and each of the other two opposite side faces forms a vertical engaging portion extending vertically. Each of the side faces of the third linkage brick forms a vertical engaging groove extending vertically. Each of the traverse engaging grooves of the first linkage brick is used to engage with each of the traverse engaging protrusions of the second linkage brick through lateral sliding.

Abstract: The present invention relates to a method for purifying polyunsaturated fatty acid using a continuous reactor, and the method comprises: (a) complexing step, (b) cleaning step, (c) extracting step, and (d) concentrating and drying step. The method of the present invention reacts a polyunsaturated fatty acid and a silver salt aqueous solution in a continuous reactor to form a complex of the polyunsaturated fatty acid and silver, and then cleans the complex with a first organic solvent to improve the purity of the complex; afterwards, a second organic solvent is used to extract the purified polyunsaturated fatty acid. The method of the present invention can continuously produce polyunsaturated fatty acids with high yield and high purity.

Abstract: A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.