Patents by Inventor Yen-Chang Hu
Yen-Chang Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11133274Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.Type: GrantFiled: June 29, 2020Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
-
Patent number: 11101192Abstract: Disclosed herein is a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.Type: GrantFiled: December 24, 2018Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Sen Chang, Tsung-Hsien Chiang, Yen-Chang Hu, Ching-Wen Hsiao
-
Publication number: 20200328169Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.Type: ApplicationFiled: June 29, 2020Publication date: October 15, 2020Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
-
Patent number: 10700025Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.Type: GrantFiled: June 8, 2016Date of Patent: June 30, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
-
Publication number: 20190148264Abstract: Disclosed herein is a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.Type: ApplicationFiled: December 24, 2018Publication date: May 16, 2019Inventors: Wei Sen Chang, Tsung-Hsien Chiang, Yen-Chang Hu, Ching-Wen Hsiao
-
Patent number: 10177073Abstract: Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.Type: GrantFiled: July 3, 2017Date of Patent: January 8, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Sen Chang, Tsung-Hsien Chiang, Yen-Chang Hu, Ching-Wen Hsiao
-
Patent number: 10157884Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.Type: GrantFiled: June 24, 2016Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Shien Chen, Yen-Chang Hu
-
Publication number: 20180286787Abstract: A method of packaging a semiconductor die includes connecting an interposer frame directly to a substrate, wherein the interposer frame has a plurality of conductive columns. The method further includes attaching the semiconductor die to the substrate in an opening of the interposer frame, wherein the semiconductor die directly contacts the substrate. The method further includes forming a molding compound to fill space between the semiconductor die and the interposer frame. The method further includes removing a portion of the molding compound to expose the plurality of conductive columns. The method further includes forming a redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame.Type: ApplicationFiled: June 4, 2018Publication date: October 4, 2018Inventors: Hui-Min HUANG, Yen-Chang HU, Chih-Wei LIN, Ming-Da CHENG, Chung-Shi LIU, Chen-Shien CHEN
-
Patent number: 9991190Abstract: The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management.Type: GrantFiled: May 18, 2012Date of Patent: June 5, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Min Huang, Yen-Chang Hu, Chih-Wei Lin, Ming-Da Cheng, Chung-Shi Liu, Chen-Shien Chen
-
Patent number: 9799620Abstract: A method of forming a die package includes forming a conductive column over a first side of a carrier, attaching a semiconductor die to the first side of the carrier, and forming a molding compound over the first side of the carrier. The semiconductor die and the conductive column are embedded in the molding compound. A second side of the carrier opposite the first side is under a compressive stress. The method also includes forming a first compressive dielectric layer over the semiconductor die, the conductive column, and the molding compound, forming a first redistribution layer (RDL) over the first compressive dielectric layer, and forming a first passivation layer over the first RDL.Type: GrantFiled: June 30, 2015Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Huang, Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
-
Publication number: 20170301608Abstract: Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.Type: ApplicationFiled: July 3, 2017Publication date: October 19, 2017Inventors: Wei Sen Chang, Tsung-Hsien Chiang, Yen-Chang Hu, Ching-Wen Hsiao
-
Patent number: 9735087Abstract: Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.Type: GrantFiled: September 20, 2012Date of Patent: August 15, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Sen Chang, Tsung-Hsien Chiang, Yen-Chang Hu, Ching-Wen Hsiao
-
Publication number: 20160307876Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Chen-Hua Yu, Chen-Shien Chen, Yen-Chang Hu
-
Patent number: 9418969Abstract: Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.Type: GrantFiled: May 8, 2015Date of Patent: August 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
-
Patent number: 9379078Abstract: A package includes package includes a first package component including a first plurality of electrical connectors at a top surface of the first package component, and a second plurality of electrical connectors longer than the first plurality of electrical connectors at the top surface of the first package component. A first device die is over the first package component and bonded to the first plurality of electrical connectors. A second package component is overlying the first package component and the first device die. The second package component includes a third plurality of electrical connectors at a bottom surface of the second package component. The third plurality of electrical connectors is bonded to the second plurality of electrical connectors. A fourth plurality of electrical connectors is at a bottom surface of the second package. The second and the fourth plurality of electrical connectors comprise non-solder metallic materials.Type: GrantFiled: November 7, 2013Date of Patent: June 28, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Shien Chen, Yen-Chang Hu
-
Patent number: 9368460Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.Type: GrantFiled: July 9, 2013Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
-
Publication number: 20150303158Abstract: A method of forming a die package includes forming a conductive column over a first side of a carrier, attaching a semiconductor die to the first side of the carrier, and forming a molding compound over the first side of the carrier. The semiconductor die and the conductive column are embedded in the molding compound. A second side of the carrier opposite the first side is under a compressive stress. The method also includes forming a first compressive dielectric layer over the semiconductor die, the conductive column, and the molding compound, forming a first redistribution layer (RDL) over the first compressive dielectric layer, and forming a first passivation layer over the first RDL.Type: ApplicationFiled: June 30, 2015Publication date: October 22, 2015Inventors: Yu-Chih Huang, Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
-
Patent number: 9165887Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.Type: GrantFiled: September 10, 2012Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Yen-Chang Hu
-
Publication number: 20150243636Abstract: Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.Type: ApplicationFiled: May 8, 2015Publication date: August 27, 2015Inventors: Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
-
Patent number: 9087832Abstract: Various embodiments of mechanisms for forming a die package and a package on package (PoP) structure using one or more compressive dielectric layers to reduce warpage are provided. The compressive dielectric layer(s) is part of a redistribution structure of the die package and its compressive stress reduces or eliminates bowing of the die package. In addition, the one or more compressive dielectric layers improve the adhesion between redistribution structure and the materials surrounding the semiconductor die. As a result, the yield and reliability of the die package and PoP structure using the die package are improved.Type: GrantFiled: March 8, 2013Date of Patent: July 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Huang, Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen