Abstract: A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.

Abstract: A memory device that includes a memory array and a pre-charge selecting circuit is introduced. The memory array includes a plurality of memory cells that are coupled to a plurality of bit lines and a plurality of word lines, wherein the plurality of word lines are configured to receive an input vector. The pre-charge selecting circuit is configured to selectively pre-charge a selected bit line according to a value of the input vector. The pre-charge selecting circuit is configured to determine whether the value of the input vector is less than a predefined threshold, and generate a gated pre-charge signal to skip pre-charging the selected bit line in response to determining that the value of the input vector is less than the predefined threshold.

Abstract: Memory circuits that read the bit state of memory cells are disclosed. In some embodiments, a memory circuit, includes a memory cell configured to store a bit. A reference line is configured to receive a reference signal and a data line is configured to receive a data signal. The data line is configured to be selectively coupled to the memory cell. A charge voltage select unit is configured to charge the reference line and the data line in response to a select signal being in a first select state and discharge the reference line and the data line in response to the select signal being in a second select state. A sense amplifier is configured to compare the data signal and the reference signal to sense a bit state of the bit stored by the memory cell.

Abstract: A memory device includes a current source and a memory array. The current source is configured to provide a current to a first node. The memory array is coupled to the current source at the first node. The memory array includes memory cells. First terminals of the memory cells are coupled to the first node. Each of the memory cells has a first resistance in response to having a first data value, and has a second resistance in response to having a second data value. The second data value is N times the first data value. The second resistance is approximately one-Nth of the first resistance, for N being a positive integer larger than one. A method of operating a memory device is also disclosed herein.

Abstract: A method, device, and system for performing a partial sum accumulation of a product of input vectors and weight vectors in a wordwise-input and bitwise-weight manner results in a partial accumulated product sum. The partial accumulated product sum is compared with a threshold condition after each weight bit, and when the partial accumulated product sum meets the threshold condition, a skip indicator is asserted to indicate that remaining computations of a sum accumulation are skipped.

Abstract: A memory includes a memory device, a reading device and a feedback device. The memory device stores a plurality of bits. The reading device includes first and second reading circuits coupled to the memory device. The second reading circuit is coupled to the first reading circuit at a first node. The first and second reading circuits cooperates with each other to generate a first voltage signal at the first node based on at least one first bit of the plurality of bits. The feedback device adjusts at least one of the first reading circuit or the second reading circuit based on the first voltage signal. The first and second reading circuits generate a second voltage signal, different from the first voltage signal, corresponding to the bits, after the at least one of the first reading circuit or the second reading circuit is adjusted by the feedback device.

Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.

Abstract: An input sequence re-ordering method with a multi input-precision reconfigurable scheme and a pipeline scheme for a computing-in-memory macro in a convolutional neural network application is configured to re-order a plurality of multi-bit input signals and includes performing a scanning step and a re-ordering step. The scanning step includes driving a scanner to scan one group of the multi-bit input signals to determine whether an initial value of a plurality of flag signals in one of a plurality of multi-bit section flags is changed to an inverted initial value according to a plurality of bit numbers of the one group of the multi-bit input signals. The re-ordering step includes driving a sorter to select a part of the one group of the multi-bit input signals corresponding to a plurality of the inverted initial values of the flag signals in the one of the multi-bit section flags.