Abstract: An insulated gate bipolar transistor (IGBT) structure including a substrate and a first gated PNPN diode is provided. The first gated PNPN diode is located on the substrate. The first gated PNPN diode includes a first gate, a first source/drain extension (SDE) region, and a second SDE region. The first gate is located on the substrate. The first SDE region and the second SDE region are located in the substrate on two sides of the first gate.

Abstract: An insulated gate bipolar transistor (IGBT) structure including a substrate and a first gated PNPN diode is provided. The first gated PNPN diode is located on the substrate. The first gated PNPN diode includes a first gate, a first source/drain extension (SDE) region, and a second SDE region. The first gate is located on the substrate. The first SDE region and the second SDE region are located in the substrate on two sides of the first gate.

Abstract: A non-volatile memory cell, a NAND-type non-volatile memory, and a method of manufacturing the same are provided. The method of manufacturing the non-volatile memory cell includes the following steps. An insulating layer, a first conductive layer, an inter-gate insulating layer, a second conductive layer, and a hard mask layer are formed on a substrate in order. The hard mask layer, the second conductive layer, the inter-gate insulating layer, and the first conductive layer are patterned to form a stacked gate structure. The insulating layer on the substrate at two sides of the stacked gate structure is removed until the surface of the substrate is exposed. A portion of the substrate at two sides of the stacked gate structure is removed to form two recesses in the substrate, and each of the recesses is extended below the stacked gate structure. A source/drain region is formed in the substrate below the recesses.