Abstract: A memory device has a memory cell operated in a first power domain having a first voltage level. A memory word line is connected to the memory cell, and a memory bit line is connected to the memory cell. A word line decoder circuit is operated in the first power domain, and a word line driver circuit is configured to receive a row address signal from the word line decoder circuit and output a word line enable signal to the memory word line. An IO circuit is connected to the memory bit line, and the IO circuit is operated in a second power domain having a second voltage level lower than the first voltage level. A tracking word line is connected to a tracking cell, and the tracking word line is configured to output a tracking cell enable signal in the first power domain. A tracking bit line is connected to the tracking cell, and the tracking bit line is configured to output a trigger signal in the first power domain to the IO circuit.

Abstract: A memory circuit includes a substrate with a front side and a back side opposite the front side. An interconnect structure is situated on or over the substrate and has first and second metal layers and a via electrically connecting the first and second metal layers. A word line driver circuit is configured to output a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit configured to receive a word line signal, and an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via.

Abstract: A memory unit includes at least one memory cell and a computational cell. The at least one memory cell stores a weight. The at least one memory cell is controlled by a first word line and includes a local bit line transmitting the weight. The computational cell is connected to the at least one memory cell and receiving the weight via the local bit line. Each of an input bit line and an input bit line bar transmits a multi-bit input value. The computational cell is controlled by a second word line and an enable signal to generate a multi-bit output value on each of an output bit line and an output bit line bar according to the multi-bit input value multiplied by the weight. The computational cell is controlled by a first switching signal and a second switching signal for charge sharing.

Abstract: A transpose memory unit for a plurality of multi-bit convolutional neural network based computing-in-memory applications includes a memory cell and a transpose cell. The memory cell stores a weight. The transpose cell is connected to the memory cell and receives the weight from the memory cell. The transpose cell includes an input bit line, at least one first input word line, a first output bit line, at least one second input word line and a second output bit line. One of the at least one first input word line and the at least one second input word line transmits at least one multi-bit input value, and the transpose cell is controlled by the second word line to generate a multiply-accumulate output value on one of the first output bit line and the second output bit line according to the at least one multi-bit input value multiplied by the weight.

Abstract: A memory unit includes at least one memory cell and a computational cell. The at least one memory cell stores a weight. The at least one memory cell is controlled by a first word line and includes a local bit line transmitting the weight. The computational cell is connected to the at least one memory cell and receiving the weight via the local bit line. Each of an input bit line and an input bit line bar transmits a multi-bit input value. The computational cell is controlled by a second word line and an enable signal to generate a multi-bit output value on each of an output bit line and an output bit line bar according to the multi-bit input value multiplied by the weight. The computational cell is controlled by a first switching signal and a second switching signal for charge sharing.

Abstract: A transpose memory unit for a plurality of multi-bit convolutional neural network based computing-in-memory applications includes a memory cell and a transpose cell. The memory cell stores a weight. The transpose cell is connected to the memory cell and receives the weight from the memory cell. The transpose cell includes an input bit line, at least one first input word line, a first output bit line, at least one second input word line and a second output bit line. One of the at least one first input word line and the at least one second input word line transmits at least one multi-bit input value, and the transpose cell is controlled by the second word line to generate a multiply-accumulate output value on one of the first output bit line and the second output bit line according to the at least one multi-bit input value multiplied by the weight.

Abstract: A junction box for a solar module is disclosed and comprises a housing having an opening for introducing a plurality of conductor strips; and an electrical connection mechanism disposed in a receptacle of the housing. The electrical connection mechanism comprises a plurality of conductor strip connection devices disposed on an inner surface of the housing for connecting to the conductor strips; and a current-path arrangement module detachably connected with the conductor strip connection devices and comprising a carrier, a plurality of electricity conveying elements and a plurality of electronic components, wherein the electricity conveying elements and the electronic components are disposed on one surface of the carrier, and each electronic component is connected with two adjacent electricity conveying elements.

Abstract: A junction box for a solar module is disclosed and comprises a housing having an opening for introducing a plurality of conductor strips; and an electrical connection mechanism disposed in a receptacle of the housing. The electrical connection mechanism comprises a plurality of conductor strip connection devices disposed on an inner surface of the housing for connecting to the conductor strips; and a current-path arrangement module detachably connected with the conductor strip connection devices and comprising a carrier, a plurality of electricity conveying elements and a plurality of electronic components, wherein the electricity conveying elements and the electronic components are disposed on one surface of the carrier, and each electronic component is connected with two adjacent electricity conveying elements.

Abstract: A conductor strip connection device for a junction box of a solar module is disclosed and comprises a contact member and a press-fitting member. The contact member has a contact segment for connecting to a conductor strip and having at least one first engaging element. The press-fitting member has a suppressing part and at least one second engaging element, wherein the suppressing part is configured to cooperate with the contact segment of the contact member for securing the conductor strip, and the second engaging element is configured to engage with the first engaging element of the contact member for assembling the press-fitting member with the contact member.

Abstract: A conductor strip connection device for a junction box of a solar module is disclosed and comprises a contact member and a press-fitting member. The contact member has a contact segment for connecting to a conductor strip and having at least one first engaging element. The press-fitting member has a suppressing part and at least one second engaging element, wherein the suppressing part is configured to cooperate with the contact segment of the contact member for securing the conductor strip, and the second engaging element is configured to engage with the first engaging element of the contact member for assembling the press-fitting member with the contact member.