Patents by Inventor Yen-Chien Lai

Yen-Chien Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Timing skew characterization apparatus and method
    Patent number: 10024906
    Abstract: A device comprises a coarse timing skew characterization circuit having a buffer chain and a coarse delay cell calibration circuit comprising a first flip-flop, a second flip-flop and a logic gate, wherein the coarse delay cell calibration circuit is configured to measure a delay between an input of the buffer chain and an output of the buffer chain.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao Kai Chuang, Yen-Chien Lai, Hung-Jen Liao
  • Timing Skew Characterization Apparatus and Method
    Publication number: 20150069994
    Abstract: A device comprises a coarse timing skew characterization circuit having a buffer chain and a coarse delay cell calibration circuit comprising a first flip-flop, a second flip-flop and a logic gate, wherein the coarse delay cell calibration circuit is configured to measure a delay between an input of the buffer chain and an output of the buffer chain.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 12, 2015
    Inventors: Chao Kai Chuang, Yen-Chien Lai, Hung-Jen Liao
  • Timing skew characterization apparatus and method
    Patent number: 8907681
    Abstract: A timing skew characterization apparatus comprises a coarse timing skew characterization circuit, a fine timing skew characterization circuit and a coarse delay cell calibration circuit. The coarse timing skew characterization circuit comprises a plurality of coarse delay cells whose delays can be calibrated through the coarse delay cell calibration circuit. The calibration of fine delay cells can be implemented through a trail and error process. Both coarse delay step and fine delay step can be characterized through a single measurement setup. As a result, the timing skew characterization apparatus provides a high resolution setup and hold time measurement.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao Kai Chuang, Yen-Chien Lai, Hung-Jen Liao
  • Timing Skew Characterization Apparatus and Method
    Publication number: 20120230158
    Abstract: A timing skew characterization apparatus comprises a coarse timing skew characterization circuit, a fine timing skew characterization circuit and a coarse delay cell calibration circuit. The coarse timing skew characterization circuit comprises a plurality of coarse delay cells whose delays can be calibrated through the coarse delay cell calibration circuit. The calibration of fine delay cells can be implemented through a trail and error process. Both coarse delay step and fine delay step can be characterized through a single measurement setup. As a result, the timing skew characterization apparatus provides a high resolution setup and hold time measurement.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 13, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao Kai Chuang, Yen-Chien Lai, Hung-Jen Liao