Patents by Inventor Yen-Chih CHIU

Yen-Chih CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CHIP POWER CONSUMPTION ANALYZER AND ANALYZING METHOD THEREOF
    Publication number: 20230342529
    Abstract: Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.
    Type: Application
    Filed: June 1, 2022
    Publication date: October 26, 2023
    Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sin-Huei Li, Cheng-Hong Tsai, Chien-Cheng Wu, Yen-Chih Chiu, Hu-Cheng Jiang
  • Wiring substrate having alternating ground and signal lines in a plurality of wiring layers
    Patent number: 10453803
    Abstract: A semiconductor wiring substrate includes a first wiring layer, a second wiring layer stacked on the first wiring layer, and a dielectric layer sandwiched between the first wiring layer and the second wiring layer. The first wiring layer includes first signal lines and first grounding lines which are interleaved and spaced apart in the first wiring layer. The second wiring layer includes second signal lines and second grounding lines which are interleaved and spaced apart in the second wiring layer. An orthographic projection of one of the second signal lines to the first wiring layer is located between each two adjacent ones of the first signal lines.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 22, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hsuan Wang, Ting-Hao Wang, Yen-Chih Chiu
  • SEMICONDUCTOR PACKAGE DEVICE AND ITS SEMICONDUCTOR WIRING SUBSTRATE
    Publication number: 20180366416
    Abstract: A semiconductor wiring substrate includes a first wiring layer, a second wiring layer stacked on the first wiring layer, and a dielectric layer sandwiched between the first wiring layer and the second wiring layer. The first wiring layer includes first signal lines and first grounding lines which are interleaved and spaced apart in the first wiring layer. The second wiring layer includes second signal lines and second grounding lines which are interleaved and spaced apart in the second wiring layer. An orthographic projection of one of the second signal lines to the first wiring layer is located between each two adjacent ones of the first signal lines.
    Type: Application
    Filed: October 31, 2017
    Publication date: December 20, 2018
    Inventors: Ming-Hsuan WANG, Ting-Hao WANG, Yen-Chih CHIU