Patents by Inventor Yen Chiu Kuo

Yen Chiu Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021431
    Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 11776818
    Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
  • Publication number: 20210257218
    Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 19, 2021
    Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
  • Publication number: 20210118689
    Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 10985028
    Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 10755972
    Abstract: A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a dielectric layer over the etch stop layer, and placing a hardmask of a material such as titanium nitride over the dielectric layer. Openings are formed to the etch stop layer, the hardmask material is selectively removed, and the openings are then the material of the etch stop layer is then selectively removed to extend the openings through the etch stop layer.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Yu-Li Cheng, Chun-Hung Chao
  • Patent number: 10354913
    Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Chun-Hung Chao, Yu-Li Cheng
  • Publication number: 20180350664
    Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.
    Type: Application
    Filed: November 1, 2017
    Publication date: December 6, 2018
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Chun-Hung Chao, Yu-Li Cheng
  • Publication number: 20180151421
    Abstract: A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a dielectric layer over the etch stop layer, and placing a hardmask of a material such as titanium nitride over the dielectric layer. Openings are formed to the etch stop layer, the hardmask material is selectively removed, and the openings are then the material of the etch stop layer is then selectively removed to extend the openings through the etch stop layer.
    Type: Application
    Filed: March 20, 2017
    Publication date: May 31, 2018
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Yu-Li Cheng, Chun-Hung Chao
  • Patent number: 8017517
    Abstract: A method and system for forming dual damascene structures in a semiconductor package. In one embodiment, the method includes forming an intermediate dielectric layer on a bottom stop layer; forming an ashing removable dielectric layer on the intermediate dielectric layer; forming a patterned photoresist layer above the ashing removable dielectric layer in the semiconductor structure; and defining an in-situ hard mask in the ashing removable dielectric layer having an opening with a profile selected from the group consisting of a via, a trench, or a combination thereof. The profile of the in-situ mask preferably is capable of being transferred to the intermediate dielectric layer by etching.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: September 13, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yen Chiu Kuo
  • Publication number: 20080305639
    Abstract: A method and system for forming dual damascene structures in a semiconductor package. In one embodiment, the method includes forming an intermediate dielectric layer on a bottom stop layer; forming an ashing removable dielectric layer on the intermediate dielectric layer; forming a patterned photoresist layer above the ashing removable dielectric layer in the semiconductor structure; and defining an in-situ hard mask in the ashing removable dielectric layer having an opening with a profile selected from the group consisting of a via, a trench, or a combination thereof. The profile of the in-situ mask preferably is capable of being transferred to the intermediate dielectric layer by etching.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Yen Chiu Kuo