Patents by Inventor Yen Chuang

Yen Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12369307
    Abstract: A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Yen Chuang, Chia Ling, Katherine H. Chiang, Chung-Te Lin
  • Patent number: 12369328
    Abstract: A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Yen Chuang, Katherine H. Chiang
  • Patent number: 12363919
    Abstract: A disclosed capacitor structure includes a support structure including a plurality of elongated structures each extending along a longitudinal direction, a transverse direction, and a vertical direction. The plurality of elongated structures includes an alternating stack of first dielectric layers and second dielectric layers, a bottom electrode formed over the support structure, a third dielectric layer formed over the bottom electrode, and a top electrode formed over the third dielectric layer. Each of the first dielectric layers includes a first width along the transverse direction and each of the second dielectric layers includes a second width along the transverse direction. In various embodiments, the first width may be less than the second width such that each of the plurality of elongated structures include walls including a corrugated width profile as a function of distance along the vertical direction. The capacitor structure may be formed in a BEOL process.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yun-Feng Kao, Ming-Yen Chuang, Katherine H. Chiang, Chien-Hao Huang
  • Publication number: 20250196398
    Abstract: A recycling processing method for wind turbine blades, which uses an acidic degradation solution for recycling waste material from wind turbine blades, mainly using a hardware design that involves immersing waste material comprising composite material of fiberglass or carbon fiber in the acidic degradation solution, effectively causing the composite waste material to swell and separate to form degradable glass fiber cloth, which is finally cleaned and dried to achieve a glass fiber cloth with no surface residual glue and a resin degreasing rate of 99.6%. Accordingly, effectively achieving recyclables by carrying out a degradation process at normal temperature to save hardware costs, and enabling reclaiming the degradation solution using fractionation by distillation, which can then be reused. Hence, the recycling processing method has the advantages of involving a simple manufacturing process, high efficiency, and the ability to process waste materials on-site, without bearing the high cost of transportation.
    Type: Application
    Filed: December 13, 2024
    Publication date: June 19, 2025
    Inventor: Wen-Yen CHUANG
  • Publication number: 20250182809
    Abstract: An integrated circuit includes an array of word lines, and an array of memory cells configured to receive selection signals from the array of word lines. Each memory cell in the array of memory cells is connected to one or more data lines in a set of data lines. The integrated circuit also includes a read-write driver configured to store into the selected memory cell a second bit value which is a bit inversion of the stored bit value.
    Type: Application
    Filed: February 3, 2025
    Publication date: June 5, 2025
    Inventors: Ming-Yen CHUANG, Katherine H. CHIANG
  • Patent number: 12324199
    Abstract: The present disclosure describes a semiconductor device with a fill structure. The semiconductor structure includes first and second fin structures on a substrate, an isolation region on the substrate and between the first and second fin structures, a first gate structure disposed on the first fin structure and the isolation region, a second gate structure disposed on the second fin structure and the isolation region, and the fill structure on the isolation region and between the first and second gate structures. The fill structure includes a dielectric structure between the first and second gate structures and an air gap enclosed by the dielectric structure. The air gap is below top surfaces of the first and second fin structures.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Yung Lin, Yen Chuang, Min-Hao Hong
  • Patent number: 12283635
    Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.
    Type: Grant
    Filed: February 20, 2024
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Katherine H. Chiang, Neil Quinn Murray, Ming-Yen Chuang, Chung-Te Lin
  • Publication number: 20250056840
    Abstract: A semiconductor device includes a substrate. Semiconductor channel layers are over the substrate. A gate structure wraps around each of the semiconductor channel layers. Source/drain epitaxial structures are on opposite sides of the gate structure. Epitaxial seed layers are below the source/drain epitaxial structures, respectively, in which a lattice constant of the epitaxial seed layers is different from a lattice constant of the source/drain epitaxial structures. Isolation layers are over the substrate and vertically below the epitaxial seed layers, respectively.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yen CHUANG
  • Publication number: 20250048716
    Abstract: Embodiments utilize a silicon germanium layer deposited to a low germanium percentage under a substrate. The substrate is used to form a field effect transistor FET structure. After formation of the FET, the silicon germanium layer is oxidized to drive germanium to a concentrated sublayer of the silicon germanium layer. The sublayer is used as a stop layer to remove the oxidized portion of the silicon germanium layer.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 6, 2025
    Inventors: Yen Chuang, Ji-Yin Tsai, Jet-Rung Chang, Zheng Hui Lim, Ta-Chun Ma
  • Publication number: 20250048689
    Abstract: Methods of forming a stacked transistor are provided. One representative method may include patterning a first dummy nanostructure, a second dummy nanostructure, and a semiconductor nanostructure. The semiconductor nanostructure may be disposed between the first dummy nanostructure and the second dummy nanostructure. The first dummy nanostructure may comprise a first semiconductor material and the second dummy nanostructure may comprise a superlattice structure. The representative method may also include performing an etching process that simultaneously recesses the first dummy nanostructure to form a sidewall recess and removes the second dummy nanostructure to form an opening. The etching process selectively etches the superlattice structure at a faster rate than the first semiconductor material. The representative method may further include forming an inner spacer and an isolation structure in, respectively, the sidewall recess and the opening.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 6, 2025
    Inventors: Ji-Yin Tsai, Zheng Hui Lim, Yen Chuang, Jet-Rung Chang, Ta-Chun Ma, Chii-Horng Li
  • Patent number: 12217785
    Abstract: An integrated circuit includes an array of word lines, and an array of memory cells configured to receive selection signals from the array of word lines. Each memory cell in the array of memory cells is connected to one or more data lines in a set of data lines. The integrated circuit also includes a read-write driver which is connected to the set of data lines and is configured to receive a flip-refresh control signal. The read-write driver has a catch circuit configured to store a first bit value related to a stored bit value in a selected memory cell. The read-write driver is configured to store into the selected memory cell a second bit value which is a bit inversion of the stored bit value.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Yen Chuang, Katherine H. Chiang
  • Publication number: 20250031435
    Abstract: In an embodiment, a method includes: patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure, the dummy nanostructure including doped silicon; forming an opening between the lower semiconductor nanostructure and the upper semiconductor nanostructure by etching the doped silicon of the dummy nanostructure; forming an isolation structure in the opening; and depositing a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 23, 2025
    Inventors: Chun Wei Chen, Zheng Hui Lim, Yen Chuang, Shun-Siang Jhan, Yi-Ching Hung, Ji-Yin Tsai
  • Publication number: 20250022934
    Abstract: Thermal stability of a transistor is improved in different ways. An interfacial layer between a source/drain electrode and a semiconductor layer is formed from a material having a higher bond dissociation energy than indium oxide. Alternatively, the interfacial layer is formed from a metal-doped oxide semiconductor material. As another option, a metal layer or a metal oxide layer is formed between the source/drain electrode and the interfacial layer.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Kuo-Chang Chiang, Katherine H. cHIANG, Yen-Chung Ho, Ming-Yen Chuang, Chung-Te Lin
  • Patent number: 12192486
    Abstract: Various schemes pertaining to video coding parallelization techniques are described. An apparatus receives video data. The apparatus subsequently calculates a plurality of figures of merits (FOMs), each of the FOM representing how well a particular coding tool may perform in encoding the video data. The apparatus further determines a coding tool that may be suitable for encoding the video data by comparing the FOMs. In determining the coding tool, the apparatus utilizes time-interleaving techniques to parallelly process the video data. The video data may include an array of coding blocks, and the apparatus may receive the video data using a snake-like processing order scanning through the array of coding blocks.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: January 7, 2025
    Assignee: MediaTek Inc.
    Inventors: Cheng-Yen Chuang, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20240413247
    Abstract: A reduced interfacial defect density and low contact resistance can be provided for a thin film transistor by using a compositionally-modulated capping layer. A stack including a gate electrode, a gate dielectric layer, an active layer including a semiconducting metal oxide material, an in-process capping layer including a dielectric metal oxide material can be formed over a substrate. A dielectric material layer can be formed, and a source cavity and a drain cavity can be formed through the dielectric material layer. Exposed portions of the in-process capping layer can be converted into conductive material portions to provide a compositionally-modulated capping layer, which includes a first conductive capping material portion, the second conductive capping material portion, and a dielectric capping material portion.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 12, 2024
    Inventors: Kuo-Chang Chiang, Katherine H. Chiang, Yen-Chung Ho, Ming-Yen Chuang, Chung-Te Lin
  • Publication number: 20240398696
    Abstract: This invention provides a delivery object suitable for a needle-free injection equipment. A biodegradable material layer is used to encapsulate an active substance, forming an initial delivery object. Then, multiple initial delivery objects are placed within a carrier space formed by a delivery object carrier, creating a delivery object. The delivery object is placed within the needle-free injection equipment and accelerated by driving force provided by a power source, so that the delivery object has sufficient kinetic energy to be injected into the target object. The delivery object carrier and the biodegradable material layer will be consumed, decomposed, or metabolized within the target object, while releasing the active substance within the target object. Encapsulating the initial delivery object with the delivery object carrier will facilitate the acceleration of the delivery object so that the delivery object has sufficient kinetic energy to be injected into the target.
    Type: Application
    Filed: August 16, 2023
    Publication date: December 5, 2024
    Inventors: PING-YEN CHUANG, YUNG-LAN CHUANG
  • Publication number: 20240397576
    Abstract: The application provides a wireless communication method and a wireless communication device. A part of payload is pre-fetched from a host to a data buffer under a store-and-forward mode before transmission begins. When data transmission begins, the part of the payload pre-fetched in the data buffer is transmitted to an antenna. A remaining part of the payload is fetched to the data buffer under a cut-through mode for payload transmission, wherein the remaining part of the payload is sent from the data buffer to the antenna for radiation.
    Type: Application
    Filed: May 14, 2024
    Publication date: November 28, 2024
    Inventors: Hao-Hua KANG, Hui-Ping TSENG, Cheng-Ying WU, Chih-Chun KUO, Shu-Min CHENG, Chi-Han HUANG, Yang-Hung PENG, Jyh-Ding HU, Chih-Pin CHU, Chu-Ling CHANG, Yen-Hsiung TSENG, Chi-Fu KOH, Yen CHUANG
  • Publication number: 20240384406
    Abstract: A substrate processing chamber is provided. The chamber includes a substrate support having an upper surface, a reflector disposed above the substrate support, the reflector includes a body comprising an upper opening having a first diameter, and a bottom opening having a second diameter different than the first diameter, a flange protruding radially from an outer circumference of the body, wherein the flange comprises a plurality of holes. The chamber also includes a plurality of heating elements disposed around the reflector. The chamber further includes a plurality of support kits, each support kit comprising a bar member, and a first fastener removably coupled to the bar member, and a cooling plate coupled to the flange by the plurality of support kits.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Sou-Chuan CHIANG, Chia Hung LIU, Yen CHUANG
  • Publication number: 20240379735
    Abstract: A disclosed method of manufacturing a capacitor structure includes forming an alternating dielectric stack comprising first dielectric layers and second dielectric layers on a substrate and forming a trench through the alternating stack of first dielectric layers and second dielectric layers. The disclosed method includes etching the first dielectric layers from the trench to form notches between the second dielectric layers and forming a bottom electrode layer covering the first dielectric layers and the second dielectric layers. The disclosed method includes forming a third dielectric layer over the bottom electrode layer and forming a top electrode layer over the third dielectric layer.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 14, 2024
    Inventors: Yun-Feng KAO, Ming-Yen CHUANG, Katherine H. CHIANG, Chien-Hao HUANG
  • Publication number: 20240371953
    Abstract: A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 1018 cm?3. A semiconductor structure and a manufacturing method are also provided.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chuang, Chang-Lin Yang, Katherine H. CHIANG, Mauricio MANFRINI