Abstract: A micro light-emitting diode is provided. The micro light-emitting diode includes a first-type semiconductor layer having a first doping type; a light-emitting layer over the first-type semiconductor layer; a first-type electrode over the first-type semiconductor layer; a second-type semiconductor layer having a second doping type over the light-emitting layer, wherein the second doping type is different from the first doping type; a second-type electrode over the second-type semiconductor layer; and a barrier layer under the first-type semiconductor layer and away from the first-type electrode and the second-type electrode, wherein the barrier layer includes a doped region having the second doping type.

Abstract: An electronic device includes a device body and an antenna module disposed in the device body and including a conductive structure and a coaxial cable including a core wire, a shielding layer wrapping the core wire, and an outer jacket wrapping the shielding layer. The conductive structure includes a structure body and a slot formed on the structure body and penetrating the structure body in a thickness direction of the structure body. A section of the shielding layer extends from the outer jacket and is connected to the structure body. A physical portion of the structure body and the section of the shielding layer are respectively located on two opposite sides of the slot in a width direction of the slot. A section of the core wire extends from the section of the shielding layer and overlaps the slot and the physical portion in the thickness direction.

Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.

Abstract: A liquid cooling heat dissipation substrate structure with partial compression reinforcement is provided. The liquid cooling heat dissipation substrate structure with partial compression reinforcement includes a heat dissipation base that integrally has a heat dissipation main structure and a compression reinforcement structure. The heat dissipation main structure and the compression reinforcement structure are formed through different processes. The heat dissipation main structure and the compression reinforcement structure have different metallographic microstructures. Crystallites of the metallographic microstructure of the heat dissipation main structure are not all arranged in one specific direction, and crystallites of the metallographic microstructure of the compression reinforcement structure are stacked and arranged in a direction that is perpendicular to a compression direction.

Abstract: A liquid cooling heat dissipation substrate with partial compression reinforcement is provided. The liquid cooling heat dissipation substrate with partial compression reinforcement includes a heat dissipation base and a compression reinforcement structure. The heat dissipation base integrally has an upper surface and a lower surface opposite to each other, and the compression reinforcement structure is partially formed on at least one of the upper surface and the lower surface. A ratio of a sum of an area of an orthogonal projection of the compression reinforcement structure on the upper surface and an area of an orthogonal projection of the compression reinforcement structure on the lower surface to a sum of an area of the upper surface and an area of the lower surface is from 10% to 60%.

Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

Abstract: A method of preparing a layout for manufacturing a semiconductor device includes receiving a layout that includes a plurality of metal interconnects, identifying a first set of metal interconnects from the metal interconnects corresponding to a first patterning process and a second set of metal interconnects from the metal interconnects corresponding to a second patterning process, identifying a first set of floating metal portions in the first set of metal interconnects and a second set of floating metal portions in the second set of metal interconnects, and removing the second set of floating metal portions from the layout, while the first set of floating metal portions remains in the layout.

Abstract: Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.

Abstract: A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

Abstract: A dual-column office table includes two oppositely disposed stationary upright columns with a connecting rod transversely connected therebetween, two guiding columns separately disposed in the two stationary upright columns, at least one steel ball sleeve fitted on either guiding column, two driving units separately disposed in the two guiding columns, and a table top to which a top portion of each guiding column is fixedly connected. A bottom end of each guiding column is provided with a limiting structure protruding outward. A bottom end of the each driving unit is fixed to a respective table base provided at bottom portion of each stationary upright column. The table top has a bottom surface fixedly connected with a fixing seat and is provided with a lifting control switch, the lifting control switch being connected with the driving units and having an end disposed in the fixing seat.