Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

Abstract: A transmitter and a method for dynamically setting a current mode of the transmitter are provided. The transmitter includes a digital signal processing (DSP) circuit and a radio frequency (RF) circuit. The DSP circuit is configured to determine a target current mode by selecting one of multiple candidate current modes of the transmitter according to instantaneous transmitting (TX) information, wherein the instantaneous TX information includes at least one of a resource block (RB) information, a modulation and coding scheme (MCS), and an orthogonal frequency-division multiplexing (OFDM) type of an instantaneous TX signal. The RF circuit is configured to output the instantaneous TX signal, wherein at least one supply voltage and at least one bias voltage of a power amplifier (PA) of the RF circuit is controlled according to the target current mode. More particularly, the multiple candidate current modes correspond to different target power consumptions of the transmitter, respectively.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes an insulating layer over the substrate. The semiconductor device structure includes a first gate structure and a second gate structure embedded in the insulating layer. The first gate structure is wider than the second gate structure, the first gate structure includes a first gate dielectric layer and a first gate electrode layer over the first gate dielectric layer, the second gate structure includes a second gate dielectric layer and a second gate electrode layer over the second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer are made of a same material, and the second gate dielectric layer is thinner than the first gate dielectric layer.

Abstract: A memory device for CIM has a memory array including a plurality of memory cells arranged in an array of rows and columns. The memory cells have a first group of memory cells and a second group of memory cells. Each row of the array has a corresponding word line, with each memory cell of a row of the array coupled to the corresponding word line. Each column of the array has a corresponding bit line, with each memory cell of a column of the array coupled to the corresponding bit line. A control circuit is configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal.

Abstract: A first n-type transistor includes a first channel component, an undoped first gate dielectric layer disposed over the first channel component, and a first gate electrode disposed over the undoped first gate dielectric layer. A second n-type transistor includes a second channel component and a doped second gate dielectric layer disposed over the second channel component. The second gate dielectric layer is doped with a p-type dipole material. A second gate electrode is disposed over the second gate dielectric layer. At least one of the first n-type transistor or the second n-type transistor further includes an aluminum-free conductive layer. The aluminum-free conductive layer is disposed between the first gate dielectric layer and the first gate electrode or between the second gate dielectric layer and the second gate electrode.

Abstract: Semiconductor structures and methods are provided. An example method includes receiving a workpiece that includes a substrate, first channel members over a first region of the substrate, second channel members over a second region of the substrate, and third channel members over a third region of the substrate, depositing a first gate dielectric layer to wrap around each of the first channel members, each of the second channel members, and each of the third channel members, selectively depositing a first dipole layer to wrap around each of the third channel members, performing a first anneal process to drive a first dopant in the first dipole layer into the first gate dielectric layer around the third channel members, removing the first dipole layer, and after the removing, depositing a second gate dielectric layer to wrap around the first channel members, the second channel members, and the third channel members.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The method includes depositing a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench using an atomic layer deposition process. The method includes forming a gate electrode layer over the gate dielectric layer. The method includes removing the gate dielectric layer and the gate electrode layer outside of the wide trench and the narrow trench.

Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

Abstract: An oral pharmaceutical formulation containing an effective amount of NRC-AN-019 including its pharmaceutically acceptable salts and polymorphs thereof, by dispersing in a polymer system in a final state of subdivision to enhance oral bioavailability. It also compositions for the treatment of Chronic Myeloid Leukemia and other tumors such as head and neck cancer, prostate cancer and the like.

Abstract: A method includes forming a first trench and a second trench in a base structure. The first trench has a first aspect ratio, and the second trench has a second aspect ratio lower than the first aspect ratio. A deposition process is then performed to deposit a layer. The layer includes a first portion extending into the first trench, and a second portion extending into the second trench. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness by a first difference. The method further includes performing an etch-back process to etch the layer. After the etch-back process, the first portion has a third thickness, and the second portion has a fourth thickness. A second difference between the third thickness and the fourth thickness is smaller than the first difference.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The method includes depositing a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench using an atomic layer deposition process. The method includes forming a gate electrode layer over the gate dielectric layer. The method includes removing the gate dielectric layer and the gate electrode layer outside of the wide trench and the narrow trench.

Abstract: Disclosed are compounds of formula (I) below and pharmaceutically acceptable salts thereof: (I), in which each of variables R1, R2, R3, R4, R5, A1, A2, A3, A4, X and Y is defined herein. Also disclosed are methods for reducing the glycemic level and treating glucagon-associated disorders with a compound of formula (I) or a salt thereof and a pharmaceutical composition containing same.

Abstract: A method, apparatus, system, and computer program product for processing a query received through a network. A computer system identifies a topic in the query. The computer system identifies a set of friends of a user from a set of social media networks in which the set of the friends have an expertise in the topic identified in the query. The computer system ranks the set of the friends based on a level of the expertise of the set of the friends for the topic and an availability of the set of the friends to form a ranked set of the friends. The computer system returns results that contain the ranked set of the friends for the topic.

Abstract: Disclosed are compounds of formula (I) below and pharmaceutically acceptable salts thereof: Formula (I), in which each of variables L, R3, R4, Y, Z1, Z2 and Z3 is defined herein. Also disclosed is a method for treating a cancer with a compound of formula (I) or a salt thereof and a pharmaceutical composition containing same.

Abstract: Disclosed is a pharmaceutical composition comprising: an active ingredient of the following formula (I) or a pharmaceutically acceptable salt or solvate thereof present in an amount of 8 wt % to 30 wt %: and two or more excipients at least including a dispersant and a solubilizer present in an amount of 70 wt % to 92 wt %. Also disclosed are methods for reducing the glycemic level and treating disorders associated with glucagon with the aforesaid pharmaceutical composition.

Abstract: Predicting probable activity consequences is provided. Information is collected from data sources to identify various activities. Patterns of how any identified activity is linked with a corresponding event are detected based on analyzing the information. The patterns are indexed with data having a relationship to a particular event. Activity context information associated with a set of identified activities corresponding to the particular event is extracted from the information. A cognitive model of how the set of identified activities corresponding to the particular event are related to a set of activity consequences is generated. Probable activity consequences with degree of severity corresponding to the activity context information is predicted based on the cognitive model. A recommendation to perform a set of action steps to reduce impact of the probable activity consequences on different aspects of the activity context information associated with the set of identified activities is generated.

Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

Abstract: Disclosed are compounds of formula (I) below and pharmaceutically acceptable salts thereof, in which each of variables R1, R2, L, and Z is defined herein. Also disclosed are methods for reducing the glycemic level and treating glucagon-associated disorders with a compound of formula (I) or a salt thereof and a pharmaceutical composition containing same.

Abstract: Disclosed are compounds of formula (I) below and pharmaceutically acceptable salts thereof: Formula (I), in which each of variables L, R3, R4, Y, Z1, Z2 and Z3 is defined herein. Also disclosed is a method for treating a cancer with a compound of formula (I) or a salt thereof and a pharmaceutical composition containing same.