Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Abstract: A method for mobility enhancement in wireless communication systems is provided. The method is performed by a User Equipment (UE) configured with a first Small Data Transmission (SDT) configuration by a first cell. The method includes receiving a Radio Resource Control (RRC) release message including a suspend configuration from the first cell; transitioning to an RRC INACTIVE state in response to receiving the RRC release message; receiving, in the RRC INACTIVE state, a System Information Block Type 1 (SIB1) including a second SDT configuration from a second cell; camping on the second cell in response to receiving the SIB1 from the second cell; and while the UE is camping on the second cell, refraining from using the first SDT configuration to initiate an SDT procedure associated with the second cell in a case that the UE does not support performing the SDT procedure associated with the second cell.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.

Abstract: In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

Abstract: Systems and methods for adaptive voltage regulation are described. According to an example, a method for operating a charger may include setting, by a charger controller of the charger, a maximum regulation voltage threshold and a minimum regulation voltage threshold, the minimum regulation voltage threshold being a predetermined percentage of the maximum regulation voltage threshold, the predetermined percentage ranging from between about 90% and about 98%; setting, by the charger controller, a charger regulation voltage to the maximum regulation voltage threshold; determining, by a battery monitor, a state of charge of a battery module; and operating the charger at the maximum regulation voltage threshold until the battery module is maximally charged.

Abstract: A semiconductor device with different gate structures and a method of fabricating the same are disclosed. The a method includes forming a fin structure on a substrate, forming a thermal oxide layer on top and side surfaces of the fin structure, forming a polysilicon structure on the thermal oxide layer, doping portions of the fin structure uncovered by the polysilicon structure to form doped fin portions, forming a nitride layer on the polysilicon structure and the thermal oxide layer, forming an oxide layer on the nitride layer, doping the nitride layer with halogen ions, forming a source/drain region in the fin structure and adjacent to the polysilicon structure, and replacing the polysilicon structure with a gate structure.