Patents by Inventor YEN-HAO HUANG

YEN-HAO HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210090618
    Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.
    Type: Application
    Filed: December 10, 2020
    Publication date: March 25, 2021
    Inventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
  • Patent number: 10867642
    Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsin-Cheng Chen, Jung-Rung Jiang, Yen-Hao Huang
  • Patent number: 10804066
    Abstract: A method for routing data for an e-beam writer includes, with a switching device of the e-beam writer, receiving a packet. The method further includes, with a scheduling engine of the switching device, routing the packet to one of a plurality of output buffers, wherein the routing is based on availabilities of the plurality of output buffers and vacancy levels of memory devices associated with the plurality of output buffers. The method further includes, with the switching device, outputting the packet from an output port associated with a memory device to which the packet is routed.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jensen Yang, Shy-Jay Lin, Yen-Hao Huang
  • Publication number: 20200304133
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Sandeep Kumar GOEL, Ji-Jan CHEN, Stanley JOHN, Yun-Han LEE, Yen-Hao HUANG
  • Patent number: 10680627
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Publication number: 20200043692
    Abstract: A method for routing data for an e-beam writer includes, with a switching device of the e-beam writer, receiving a packet. The method further includes, with a scheduling engine of the switching device, routing the packet to one of a plurality of output buffers, wherein the routing is based on availabilities of the plurality of output buffers and vacancy levels of memory devices associated with the plurality of output buffers. The method further includes, with the switching device, outputting the packet from an output port associated with a memory device to which the packet is routed.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Jensen Yang, Shy-Jay Lin, Yen-Hao Huang
  • Patent number: 10446358
    Abstract: A method includes receiving, by an input buffer of a switching device, a packet, determining, by a scheduling engine of the switching device, a destination output buffer for the packet, receiving, by the scheduling engine of the switching device, an availability of the destination output buffer and a vacancy level of a memory device that is associated with the destination output buffer, and based on the availability of the destination output buffer and the vacancy level of the memory device, determining, by the scheduling engine of the switching device, a routing destination of the packet. The routing destination includes the input buffer, the destination output buffer, and the memory device.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jensen Yang, Shy-Jay Lin, Yen-Hao Huang
  • Publication number: 20190229737
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Sandeep Kumar GOEL, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Publication number: 20190139733
    Abstract: A method includes receiving, by an input buffer of a switching device, a packet, determining, by a scheduling engine of the switching device, a destination output buffer for the packet, receiving, by the scheduling engine of the switching device, an availability of the destination output buffer and a vacancy level of a memory device that is associated with the destination output buffer, and based on the availability of the destination output buffer and the vacancy level of the memory device, determining, by the scheduling engine of the switching device, a routing destination of the packet. The routing destination includes the input buffer, the destination output buffer, and the memory device.
    Type: Application
    Filed: August 14, 2018
    Publication date: May 9, 2019
    Inventors: Jensen Yang, Shy-Jay Lin, Yen-Hao Huang
  • Patent number: 10256828
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Patent number: 10049851
    Abstract: A system includes a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable; a switching device that is coupled to the DPG, the switching device configured to route a packet to the DPG so as to control at least one of the pixels, the switching device further comprising: a plurality of input buffers configured to receive and store the packet through a transmission line; a plurality of output buffers; a plurality of memory devices, wherein each of the plurality of memory devices is associated with one of the plurality of output buffers; and a scheduling engine that is coupled to the plurality of input buffers, the plurality of output buffers, and the plurality of memory devices and is configured to determine a routing path for the packet stored in one of the input buffers based on an availability of the output buffers and a vacancy level the memory devices.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jensen Yang, Shy-Jay Lin, Yen-Hao Huang
  • Publication number: 20180152193
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: September 21, 2017
    Publication date: May 31, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sandeep Kumar GOEL, Ji-Jan CHEN, Stanley JOHN, Yun-Han LEE, Yen-Hao HUANG
  • Publication number: 20170337955
    Abstract: Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write data to the random access memory. The random access memory can process commands at a first rate when the series of commands matches a pattern, and at a second, slower, rate when the series of commands does not match the pattern. A determination is made as to whether the series of commands matches the pattern based on at least a current command and a prior command in the series of commands. A ready signal is asserted when said determining determines that the series of commands matches the pattern, where the random access memory is configured to receive and process commands faster than the second rate when the pattern is matched and the ready signal is asserted over a period of multiple commands.
    Type: Application
    Filed: November 2, 2016
    Publication date: November 23, 2017
    Inventors: HSIN-CHENG CHEN, JUNG-RUNG JIANG, YEN-HAO HUANG
  • Publication number: 20170315455
    Abstract: A system includes a digital pattern generator (DPG) having a plurality of pixels that are dynamically and individually controllable; a switching device that is coupled to the DPG, the switching device configured to route a packet to the DPG so as to control at least one of the pixels, the switching device further comprising: a plurality of input buffers configured to receive and store the packet through a transmission line; a plurality of output buffers; a plurality of memory devices, wherein each of the plurality of memory devices is associated with one of the plurality of output buffers; and a scheduling engine that is coupled to the plurality of input buffers, the plurality of output buffers, and the plurality of memory devices and is configured to determine a routing path for the packet stored in one of the input buffers based on an availability of the output buffers and a vacancy level the memory devices.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventors: Jensen Yang, Shy-Jay Lin, Yen-Hao Huang
  • Publication number: 20130119302
    Abstract: An enhancing agent for increasing heat transfer efficiency is disclosed, which is an additive composed of a nano-scale powder and a micro-scale powder that is to be added into a heat-transfer fluid circulating in an heat exchange system or in a coolant circulating in a cooling system for enhancing the heat conductivity of the heat-transfer fluid or the coolant while helping the tank and the fluid passages used in those systems to maintain clean, and eventually enabling those systems to operate with improved heat dissipation effect. By adding the aforesaid enhancing agent into a cooling system of an internal-combustion engine, the heat shock inside the engine that is originated from the fuel burning in the engine can be reduced, resulting that not only the amount of green house gas emission is reduced, but also the chance of engine juddering that is generally originated from poor heat dissipation can be decreased.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 16, 2013
    Inventors: YEN-HAO HUANG, Hung-Wei Chen