Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: A process for making a low-profile choke includes steps of: providing an etchable substrate; applying a masking layer on the etchable substrate; etching the etchable substrate through perforated patterns of the masking layer to permit the etchable substrate to be formed with an array of recessed patterns, each of which includes a core recess portion and a coil-patterned recess portion; filling a magnetic material and a conductive material respectively into the core recess portion and the coil-patterned recess portion of each of the recessed patterns to form in the etchable substrate a plurality of magnetic cores and a plurality of conductive coils; and slicing the etchable substrate to obtain a plurality of choke bodies.

Abstract: A method for making a miniaturized circuit includes: depositing a bottom metal layer including a first metal on a substrate; forming a patterned photoresist layer on the bottom metal layer to expose a first portion of the bottom metal layer and to cover a second portion thereof; plating a middle circuit pattern including a second metal on the bottom metal layer to cover the first portion of the bottom metal layer; plating a top circuit pattern including a third metal different from the first metal onto the middle circuit pattern to cover the middle circuit pattern; removing the patterned photoresist layer; and etching the second portion of the bottom metal layer with an etchant, so as to pattern the bottom metal layer into a bottom circuit pattern.

Abstract: A process for making a low-profile choke includes steps of: providing an etchable substrate; applying a masking layer on the etchable substrate; etching the etchable substrate through perforated patterns of the masking layer to permit the etchable substrate to be formed with an array of recessed patterns, each of which includes a core recess portion and a coil-patterned recess portion; filling a magnetic material and a conductive material respectively into the core recess portion and the coil-patterned recess portion of each of the recessed patterns to form in the etchable substrate a plurality of magnetic cores and a plurality of conductive coils; and slicing the etchable substrate to obtain a plurality of choke bodies.

Abstract: An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a recess. The functional layered structure is formed on the chip body and includes a conductive layer that has at least a portion which covers at least partially the circuit-forming surface, and a magnetic layer that is disposed within the recess and that is inductively coupled to the conductive layer for generating inductance. A method of making the embedded passive chip device is also disclosed.

Abstract: A magnetic core inductor chip includes a core and a coil. The core is in the form of a single piece of a magnetic material. The coil is deposited on and surrounds the core and has structural characteristics indicative of the coil being formed on the core by deposition techniques. Methods for making the magnetic core inductor chip are also disclosed.

Abstract: A magnetic patterned wafer used for production of magnetic-core-inductor chip bodies includes a peripheral end portion and at least one core chip unit that including a connecting portion, a breaking line, and a plurality of spaced apart chip bodies. The connecting portion is connected to the peripheral end portion and is spaced apart from the chip bodies by a tab-accommodating space. The breaking line has a plurality of connecting tabs that are spaced apart from one another and that are disposed in the tab-accommodating space. Each of the connecting tabs interconnects the connecting portion and a respective one of the chip bodies. The patterned wafer is made from a magnetic material.

Abstract: A high frequency inductor chip includes a core and a coil. The core is in the form of a single piece of a non-magnetic material. The coil is deposited on and surrounds the core and has structural characteristics indicative of the coil being formed on the core by deposition techniques. A method for making the high frequency inductor chip is also disclosed.

Abstract: A patterned wafer used for production of passive-component chip bodies includes a peripheral end portion and at least one passive-component unit that including a connecting portion, a breaking line, and a plurality of spaced apart chip bodies. The connecting portion is connected to the peripheral end portion and is spaced apart from the chip bodies by a tab-accommodating space along a first direction. The breaking line has a plurality of connecting tabs that are spaced apart from one another and that are disposed in the tab-accommodating space. Each of the connecting tabs interconnects the connecting portion and a respective one of the chip bodies. A method for making the patterned wafer is also disclosed.

Abstract: An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a recess. The functional layered structure is formed on the chip body and includes a conductive layer that has at least a portion which covers at least partially the circuit-forming surface, and a magnetic layer that is disposed within the recess and that is inductively coupled to the conductive layer for generating inductance. A method of making the embedded passive chip device is also disclosed.

Abstract: A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed.

Abstract: An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a recess. The functional layered structure is formed on the chip body and includes a conductive layer that has at least a portion which covers at least partially the circuit-forming surface, and a magnetic layer that is disposed within the recess and that is inductively coupled to the conductive layer for generating inductance. A method of making the embedded passive chip device is also disclosed.

Abstract: A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed.

Abstract: A patterned wafer used for production of passive-component chip bodies includes a peripheral end portion and at least one passive-component unit that including a connecting portion, a breaking line, and a plurality of spaced apart chip bodies. The connecting portion is connected to the peripheral end portion and is spaced apart from the chip bodies by a tab-accommodating space along a first direction. The breaking line has a plurality of connecting tabs that are spaced apart from one another and that are disposed in the tab-accommodating space. Each of the connecting tabs interconnects the connecting portion and a respective one of the chip bodies. A method for making the patterned wafer is also disclosed.

Abstract: A magnetic patterned wafer used for production of magnetic-core-inductor chip bodies includes a peripheral end portion and at least one core chip unit that including a connecting portion, a breaking line, and a plurality of spaced apart chip bodies. The connecting portion is connected to the peripheral end portion and is spaced apart from the chip bodies by a tab-accommodating space. The breaking line has a plurality of connecting tabs that are spaced apart from one another and that are disposed in the tab-accommodating space. Each of the connecting tabs interconnects the connecting portion and a respective one of the chip bodies. The patterned wafer is made from a magnetic material.

Abstract: A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed.

Abstract: A high frequency inductor chip includes a core and a coil. The core is in the form of a single piece of a non-magnetic material. The coil is deposited on and surrounds the core and has structural characteristics indicative of the coil being formed on the core by deposition techniques. A method for making the high frequency inductor chip is also disclosed.

Abstract: An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a recess. The functional layered structure is formed on the chip body and includes a conductive layer that has at least a portion which covers at least partially the circuit-forming surface, and a magnetic layer that is disposed within the recess and that is inductively coupled to the conductive layer for generating inductance. A method of making the embedded passive chip device is also disclosed.

Abstract: A magnetic core inductor chip includes a core and a coil. The core is in the form of a single piece of a magnetic material. The coil is deposited on and surrounds the core and has structural characteristics indicative of the coil being formed on the core by deposition techniques. Methods for making the magnetic core inductor chip are also disclosed.

Abstract: HomeMeeting Inc. provides complete Internet service (www.homemeeting.com) for multipoint multimedia IP-communication network. To the best of our knowledge, this is the first attempt of fully Internet-based interactive multipoint multimedia WAN communication service with enhanced quality of service (QoS) and a complete suite of presentation/discussion functionalities over narrowband (as low as 26.4 Kbps) connections. Every registered member of this service can sign into the Member Meeting Center from HomeMeeting's website, schedule meeting, invite meeting participants, and pre-upload documents for online discussion.