Abstract: Some embodiments of the present disclosure provide a semiconductor structure including a dielectric layer stack, an isolation structure, a lining layer and a contact. The isolation structure is in contact with a sidewall of the dielectric layer stack, and the sidewall of the dielectric layer stack and a sidewall of the isolation structure define a sharp corner. The lining layer is at the sharp corner, and a sidewall of the lining layer, the sidewall of the dielectric layer stack and the sidewall of the isolation structure define a round corner. The contact is in contact with the sidewall of the dielectric layer stack, the sidewall of the isolation structure and the sidewall of the lining layer.

Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, a first isolation spacer, a second isolation spacer, a capacitor contact, a landing pad, and a dielectric structure. The bit line is disposed on the substrate. The first isolation spacer is disposed on a first side of the bit line. The second isolation spacer is disposed on a second side of the bit line. The capacitor contact is disposed on the substrate and spaced apart from the bit line through the first isolation spacer. The landing pad is disposed on the first isolation spacer and electrically connected to the capacitor contact. The dielectric structure is disposed on the second isolation contact. A top surface of the dielectric structure is non-coplanar with a top surface of the landing pad.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, a first isolation spacer, a second isolation spacer, a capacitor contact, a landing pad, and a dielectric structure. The bit line is disposed on the substrate. The first isolation spacer is disposed on a first side of the bit line. The second isolation spacer is disposed on a second side of the bit line. The capacitor contact is disposed on the substrate and spaced apart from the bit line through the first isolation spacer. The landing pad is disposed on the first isolation spacer and electrically connected to the capacitor contact. The dielectric structure is disposed on the second isolation contact. A top surface of the dielectric structure is non-coplanar with a top surface of the landing pad.

Abstract: The present invention relates to a method of manufacturing a photovoltaic device having an ultra-shallow junction layer. In the method, a crystalline silicon substrate is cleaned and a first doped semiconductor layer with 1.12 eV bandgap and 5˜80 nm of thickness is grown on the crystalline silicon substrate by high density plasma electron cyclotron resonance CVD in a preparation condition of a temperature of the crystalline silicon substrate ranging from 50° C. to 250° C. , about 500W of microwave power, deposition pressure below 50 mTorr, about 20 sccm of argon and hydrogen flow rate, SiH4 flow rate ranging from 1 sccm to 2 sccm, and 2% boroethane flow rate ranging from about 5 seem to 15 sccm. The photovoltaic device of the present invention has advantages of abrupt homo-junction, ultra-thin high-crystallinity silicon-based thin film, highly-doped concentration, high conductivity and high short-circuit current, thereby having improved efficiency.