Abstract: A semiconductor device includes a memory array. The memory array is configured to calculate first data and second data, and includes a first memory cell and a second memory cell. The first memory cell is configured to generate a first current signal at a first node, in response to the first data. The second memory cell is configured to generate a second current signal at the first node when the first memory cell generating the first current signal, in response to the second data. When the first data has a first data value and the second data has a second data value, the second memory cell is further configured cancel the first current signal with the second current signal. The second data value is a negative value of the first data value.

Abstract: A ceiling fan includes an outer shield, a middle ring, a blade bracket, and a fan blade. The middle ring is pivotally connected to the outer shield and rotates relative to the outer shield. The blade bracket protrudes from the middle ring and has two guiding surfaces located on opposite sides of the blade bracket. The fan blade is combined with the middle ring by the blade bracket. The fan blade has an opening on an end close to the blade bracket. The fan blade further includes a housing, one or more supporting ribs, and two guiding limiting parts.

Abstract: A push-pull Low Dropout (LDO) voltage regulator is provided. An instantaneous output voltage of the push-pull LDO voltage regulator is compared with a first reference voltage and a first output based on comparing the first reference voltage with the instantaneous output voltage is provided. The instantaneous output voltage of the push-pull LDO voltage regulator is compared with a second reference voltage and a second output based on comparing the instantaneous output voltage with the second reference voltage is provided. One or more bi-directional drivers of a plurality of bi-directional drivers of the push-pull LDO voltage regulator are driven based on the first output and the second output. The plurality of bi-directional drives provide the predetermined output voltage.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: A method includes forming a transistor layer; forming a first metallization layer, including: forming first conductors, aligned along alpha tracks, and representing input pins of a cell region including first and second input pins; and cutting lengths of the first and second input pins to accommodate at most two access points, each aligned to a different one of first to fourth beta tracks, the beta tracks to which are aligned the access points of the first input pin being different than the beta tracks to which are aligned the access points of the second input pin; and forming a second metallization layer, including: forming second conductors representing routing segments and a representing a power grid segment aligned with one of the beta tracks of access points of the first input pin or the access points of the second input pin.

Abstract: A light-emitting device includes: a substrate having a top surface, wherein the top surface comprises a first portion and a second portion; a first semiconductor stack on the first portion, comprising a first upper surface and a first side wall; and a second semiconductor stack on the first upper surface, comprising a second upper surface and a second side wall, and wherein the second side wall connects the first upper surface; wherein the first semiconductor stack comprises a dislocation stop layer; wherein the dislocation stop layer comprises AlGaN; and wherein the first side wall and the second portion of the top surface form an acute angle ? between thereof.

Abstract: Test equipment for a battery management system is provided. A battery-parameter recognition module measures a standard battery to obtain the first correction input, and uses the capacity test formula and the relaxation time test formula to perform a first charge and discharge test on the battery to be tested to obtain first battery parameter. A real-time simulation module determines the battery model and the simulated battery state based on the first battery parameter and the dynamic load. Each simulator of a physical signal simulation module provides a battery physical signal indicating the battery model. A connector provides the battery physical signal to the battery management controller under test. The battery management controller under test provides a stimulated battery state based on the battery physical signal. Master equipment compares the simulated battery state with an estimated battery state to determine whether the battery management controller under test is normal.

Abstract: A carriers synchronizing method of a hybrid frequency parallel inverter is proposed. A low-frequency ripple simulating step is performed to drive a high-frequency controlling unit to simulate a low-frequency ripple. An equidistant grid sampling step is performed to drive the high-frequency controlling unit to sample a sample ripple to generate a sample group and sample the low-frequency ripple to generate a plurality of low-frequency reference groups. An actual shifting angle searching step is performed to drive the high-frequency controlling unit to compare the sample group with the low-frequency reference groups to search an actual shifting angle from the reference shifting angles. A high-frequency carrier adjusting step is performed to drive a proportional integral controller to calculate the actual shifting angle to generate a sync reference, and then a period counter adjusts a starting point of the high-frequency carrier according to the sync reference.

Abstract: A carriers synchronizing method of a hybrid frequency parallel inverter is proposed. A low-frequency ripple simulating step is performed to drive a high-frequency controlling unit to simulate a low-frequency ripple. An equidistant grid sampling step is performed to drive the high-frequency controlling unit to sample a sample ripple to generate a sample group and sample the low-frequency ripple to generate a plurality of low-frequency reference groups. An actual shifting angle searching step is performed to drive the high-frequency controlling unit to compare the sample group with the low-frequency reference groups to search an actual shifting angle from the reference shifting angles. A high-frequency carrier adjusting step is performed to drive a proportional integral controller to calculate the actual shifting angle to generate a sync reference, and then a period counter adjusts a starting point of the high-frequency carrier according to the sync reference.

Abstract: An input-shaping method for a group-modulated input scheme in a plurality of computing-in-memory applications is configured to shape a plurality of multi-bit input signals. The input-shaping method for the group-modulated input scheme in the plurality of computing-in-memory applications includes performing an input splitting step, a threshold setting step and an input shaping step. The input splitting step includes splitting the multi-bit input signals into a plurality of input sub-groups via an input-shaping unit. The threshold setting step includes setting at least one shaping threshold via the input-shaping unit. The input shaping step includes shaping at least one of the input sub-groups according to the at least one shaping threshold via the input-shaping unit to form a plurality of shaped multi-bit input signals so as to increase a probability of a bit equal to 0 occurring in the at least one of the input sub-groups.

Abstract: An input-shaping method for a group-modulated input scheme in a plurality of computing-in-memory applications is configured to shape a plurality of multi-bit input signals. The input-shaping method for the group-modulated input scheme in the plurality of computing-in-memory applications includes performing an input splitting step, a threshold setting step and an input shaping step. The input splitting step includes splitting the multi-bit input signals into a plurality of input sub-groups via an input-shaping unit. The threshold setting step includes setting at least one shaping threshold via the input-shaping unit. The input shaping step includes shaping at least one of the input sub-groups according to the at least one shaping threshold via the input-shaping unit to form a plurality of shaped multi-bit input signals so as to increase a probability of a bit equal to 0 occurring in the at least one of the input sub-groups.

Abstract: A memory unit with an asymmetric group-modulated input scheme and a current-to-voltage signal stacking scheme for a plurality of non-volatile computing-in-memory applications is configured to compute a plurality of multi-bit input signals and a plurality of weights. A controller splits the multi-bit input signals into a plurality of input sub-groups and generates a plurality of switching signals according to the input sub-groups, and the input sub-groups are sequentially inputted to the word lines. The current-to-voltage signal stacking converter converts the bit-line current from a plurality of non-volatile memory cells into a plurality of converted voltages according to the input sub-groups and the switching signals, and the current-to-voltage signal stacking converter stacks the converted voltages to form an output voltage. The output voltage is corresponding to a sum of a plurality of multiplication values which are equal to the multi-bit input signals multiplied by the weights.

Abstract: A memory unit with an asymmetric group-modulated input scheme and a current-to-voltage signal stacking scheme for a plurality of non-volatile computing-in-memory applications is configured to compute a plurality of multi-bit input signals and a plurality of weights. A controller splits the multi-bit input signals into a plurality of input sub-groups and generates a plurality of switching signals according to the input sub-groups, and the input sub-groups are sequentially inputted to the word lines. The current-to-voltage signal stacking converter converts the bit-line current from a plurality of non-volatile memory cells into a plurality of converted voltages according to the input sub-groups and the switching signals, and the current-to-voltage signal stacking converter stacks the converted voltages to form an output voltage. The output voltage is corresponding to a sum of a plurality of multiplication values which are equal to the multi-bit input signals multiplied by the weights.

Abstract: A controlling method is for a single-phase bidirectional inverter. The single-phase bidirectional inverter includes a switch and an inductor. The controlling method for the single-phase bidirectional inverter includes an extracting step, a calculating step, and an integrating step. In the extracting step, a current command is inputted to the switch and obtaining a current through the inductor. The current is piecewisely linearized to extract a magnetizing inductance and a demagnetizing inductance of the inductor. In the calculating step, a duty ratio of the switch is used to calculate a variation of the current of the magnetizing inductance and a variation of the current of the demagnetizing inductance. In the integrating step, the variation of the current of the magnetizing inductance and the variation of the current of the demagnetizing inductance are integrated to obtain another duty ratio of the switch in the next cycle.

Abstract: A memory unit with multiple word lines for a plurality of non-volatile computing-in-memory applications is configured to compute a plurality of input signals and a plurality of weights. The memory unit includes a non-volatile memory cell array, a replica non-volatile memory cell array and a multi-row current calibration circuit. The non-volatile memory cell array is configured to generate a bit-line current. The replica non-volatile memory cell array includes a plurality of replica non-volatile memory cells and is configured to generate a calibration current. Each of the replica non-volatile memory cells is in the high resistance state. The multi-row current calibration circuit is electrically connected to the non-volatile memory cell array and the replica non-volatile memory cell array. The multi-row current calibration circuit is configured to subtract the calibration current from a dataline current to generate a calibrated dataline current. The dataline current is equal to the bit-line current.

Abstract: Test equipment for a battery management system is provided. A battery-parameter recognition module measures a standard battery to obtain the first correction input, and uses the capacity test formula and the relaxation time test formula to perform a first charge and discharge test on the battery to be tested to obtain first battery parameter. A real-time simulation module determines the battery model and the simulated battery state based on the first battery parameter and the dynamic load. Each simulator of a physical signal simulation module provides a battery physical signal indicating the battery model. A connector provides the battery physical signal to the battery management controller under test. The battery management controller under test provides a stimulated battery state based on the battery physical signal. Master equipment compares the simulated battery state with an estimated battery state to determine whether the battery management controller under test is normal.

Abstract: A controlling method is for a single-phase bidirectional inverter. The single-phase bidirectional inverter includes a switch and an inductor. The controlling method for the single-phase bidirectional inverter includes an extracting step, a calculating step, and an integrating step. In the extracting step, a current command is inputted to the switch and obtaining a current through the inductor. The current is piecewisely linearized to extract a magnetizing inductance and a demagnetizing inductance of the inductor. In the calculating step, a duty ratio of the switch is used to calculate a variation of the current of the magnetizing inductance and a variation of the current of the demagnetizing inductance. In the integrating step, the variation of the current of the magnetizing inductance and the variation of the current of the demagnetizing inductance are integrated to obtain another duty ratio of the switch in the next cycle.

Abstract: A power converting device with a high frequency inverter module compensating a low frequency inverter module is for transmitting a direct current voltage to an alternating current load module. The low frequency inverter module is controlled by a low frequency duty ratio. The high frequency inverter module is connected to the low frequency inverter module in parallel and controlled by a high frequency duty ratio. The low frequency inverter module is controlled according to the low frequency duty ratio to generate a first current. The high frequency duty ratio is adjusted according to a low-frequency ripple current. The high frequency inverter module is controlled according to the high frequency duty ratio to generate a second current, and the second current is for compensating ripples of the first current.

Abstract: A three phase inverting device includes a three phase inverter module and a three phase filter module. The three phase inverter module includes a plurality of switches, each two switches are connected for forming a bridge arm, an input end of each of the bridge arm are coupled for forming a DC end, the DC end is connected to a DC load. The three phase filter module is connected to the three phase inverter module, wherein the three phase filter module includes a plurality of inductances and a plurality of capacitances, the inductances are connected at one side of the capacitances, a portion of the capacitances are connected to a output end of each of the bridge arm of the three phase inverter module, a portion of the inductances are connected to an AC end.