Patents by Inventor Yen-Hsiang Lin

Yen-Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162079
    Abstract: A method of manufacturing a semiconductor device includes: forming mutually parallel three-dimensional (3D) conductive channels coated with a conformal sacrificial layer, the 3D conductive channels coated with the conformal sacrificial layer being formed on a semiconductor substrate; depositing a dielectric material to fill spaces between the 3D conductive channels coated with the conformal sacrificial layer, wherein a portion or all of the deposited dielectric material is doped with boron, lithium, or beryllium; performing chemical mechanical polishing (CMP) to remove a top portion of the deposited dielectric material and to expose tops of the 3D conductive channels; and after the CMP, removing the conformal sacrificial layer coating the 3D conductive channels by etching to form 3D dielectric features spaced apart from the 3D conductive channels and comprising the deposited dielectric material.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 16, 2024
    Inventors: Miao-Syuan Fan, Yen Chuang, Yuan-Lin Lin, Ta-Hsiang Kung
  • Patent number: 11983475
    Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen, Chin-Chou Liu, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Yi-Kan Cheng
  • Patent number: 11977251
    Abstract: A backlight module including a light guide plate, a light source, an upper prism sheet, and a lower prism sheet is provided. The light guide plate has a light incident surface and a light emitting surface. The upper prism sheet is disposed at a side of the light emitting surface of the light guide plate. The upper prism sheet includes an upper substrate and first prism microstructures. Cross-sections of the first prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 80 to 90 degrees. The lower prism sheet is disposed between the light guide plate and the upper prism sheet. The lower prism sheet includes a lower substrate and second prism microstructures. Cross-sections of the second prism microstructures are isosceles triangles, and apex angles thereof fall within a range of 100 to 130 degrees.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: May 7, 2024
    Assignee: Coretronic Corporation
    Inventors: Chun-Hsiang Hsu, Yen-Hao Lin, Wei-Hsuan Cheng
  • Publication number: 20240145379
    Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 2, 2024
    Inventors: Yen-Kun Lai, Wei-Hsiang Tu, Ching-Ho Cheng, Cheng-Nan Lin, Chiang-Jui Chu, Chien Hao Hsu, Kuo-Chin Chang, Mirng-Ji Lii
  • Patent number: 11962239
    Abstract: A control circuit of a power converter and a control method thereof are provided. The control circuit includes an error amplifier, a controller, a digital filter, and a digital pulse width signal modulator. The error amplifying circuit is coupled to an output terminal of the power converter and provides a digital error signal. The controller provides a first working parameter corresponding to the first external control command when receiving a first external control command. The digital filter generates a current digital compensation value. The digital pulse width signal modulator generates a pulse width modulation signal. The controller provides a second working parameter corresponding to the second external control command when receiving a second external control command. The controller calculates a transition value according to the second working parameter and the current digital compensation value. The controller provides the second working parameter and the transition value to the digital filter.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 16, 2024
    Assignee: uPI Semiconductor Corp.
    Inventors: Yun-Kuo Lee, Wei-Hsiang Wang, Yen-Chih Lin, Wei-Hsiu Hung
  • Patent number: 11935757
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20240087933
    Abstract: A wafer transporting method includes following operations. A plurality of wafers are received in a semiconductor container attached to a mobile vehicle. An air processing system is coupled to a wall of the semiconductor container. The air processing system includes an inlet valve, an outlet valve, a pump between the inlet valve and the outlet valve, and a desiccant coupled to the pump. The semiconductor container is moved. The pump of the air processing system is turned on to extract air from inside the semiconductor container into the air processing system through the inlet valve. Humidity of the air is reduced when the air passes through the desiccant of the air processing system. The air is returned back to the semiconductor container through the outlet valve.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: YOU-CHENG YEH, MAO-CHIH HUANG, YEN-CHING HUANG, YU HSUAN CHUANG, TAI-HSIANG LIN, JIAN-SHIAN LIN
  • Publication number: 20240085613
    Abstract: A backlight module includes a light guide plate, a light source, a first prism sheet, and a second prism sheet. The light source is disposed on a light incident surface of the light guide plate. The first prism sheet is disposed on a side of a light exiting surface of the light guide plate and has multiple first prism structures facing the light guide plate. The second prism sheet has multiple second prism structures facing the light guide plate. An included angle between an extending direction of the first prism structures and an extending direction of the second prism structures is greater than or equal to 85 degrees and less than or equal to 95 degrees. An included angle between the extending direction of the second prism structures and the light incident surface is greater than or equal to 85 degrees and less than or equal to 95 degrees.
    Type: Application
    Filed: July 26, 2023
    Publication date: March 14, 2024
    Applicants: Coretronic Optics (Suzhou) Co., Ltd., Coretronic Corporation
    Inventors: Chun-Hsiang Hsu, Yen-Hao Lin, Wen-Pin Yang
  • Patent number: 11520430
    Abstract: A touch signal processing method, for a touch display integrated device including a plurality of touch display units, is provided. Each of the plurality of touch display units includes a touch microcontroller unit (MCU). The touch signal processing method includes sensing, by a sensing module of each of the plurality of touch display units, a physical area corresponding to each of the plurality of touch display units to generate a plurality of sensing raw data; passing, by an (n?1)-th touch MCU of the plurality of touch display units, a plurality of overlap sensing raw data corresponding to an overlap area of the physical area to an n-th touch MCU; and determining, by each of the touch MCU of the plurality of touch display units, a coordinate information corresponding to a touch location of a processing area.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 6, 2022
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Li-Lin Liu, Chun-Jen Su, Wen-Sen Su, Yen-Hsiang Lin
  • Publication number: 20220244804
    Abstract: A touch signal processing method, for a touch display integrated device including a plurality of touch display units, is provided. Each of the plurality of touch display units includes a touch microcontroller unit (MCU). The touch signal processing method includes sensing, by a sensing module of each of the plurality of touch display units, a physical area corresponding to each of the plurality of touch display units to generate a plurality of sensing raw data; passing, by an (n?1)-th touch MCU of the plurality of touch display units, a plurality of overlap sensing raw data corresponding to an overlap area of the physical area to an n-th touch MCU; and determining, by each of the touch MCU of the plurality of touch display units, a coordinate information corresponding to a touch location of a processing area.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Inventors: Li-Lin Liu, Chun-Jen Su, Wen-Sen Su, Yen-Hsiang Lin