Patents by Inventor Yen-hsien Yeh
Yen-hsien Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085718Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion used for connecting an optical element, a fixed portion, and a driving assembly used for driving the movable portion to move relative to the fixed portion. The movable portion is movable relative to the fixed portion.Type: ApplicationFiled: September 7, 2023Publication date: March 14, 2024Inventors: Po-Xiang ZHUANG, Chen-Hung CHAO, Yen-Sheng LIU, Shou-Jen LIU, Yi-Ho CHEN, Yung-Hsien YEH
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Publication number: 20240077745Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion used for connecting an optical element, a fixed portion, and a driving assembly used for driving the movable portion to move relative to the fixed portion. The movable portion is movable relative to the fixed portion.Type: ApplicationFiled: September 7, 2023Publication date: March 7, 2024Inventors: Po-Xiang ZHUANG, Chen-Hung CHAO, Yen-Sheng LIU, Shou-Jen LIU, Yi-Ho CHEN, Yung-Hsien YEH
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Patent number: 8563437Abstract: The invention discloses a treating method to produce various patterns on the surface by using gases with ability to etch the group III nitride semiconductor in certain conditions. The selective etching makes some specific patterns on group III nitride semiconductor surface, and different forms of the patterns can be controlled by the selective etching conditions.Type: GrantFiled: March 16, 2011Date of Patent: October 22, 2013Assignee: National Chiao Tung UniversityInventors: Wei-I Lee, Ying-Chia Hsu, Yen-Hsien Yeh, Kuei-Ming Chen
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Patent number: 8541314Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.Type: GrantFiled: May 18, 2011Date of Patent: September 24, 2013Assignee: National Chiao Tung UniversityInventors: Wei-I Lee, Kuei-Ming Chen, Yin-Hao Wu, Yen-Hsien Yeh
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Publication number: 20130102128Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.Type: ApplicationFiled: January 10, 2012Publication date: April 25, 2013Applicant: National Chiao Tung UniversityInventors: Wei-I Lee, Yen-Hsien Yeh, Yin-Hao Wu, Tzu-Yi Yu
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Patent number: 8420543Abstract: A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device.Type: GrantFiled: January 10, 2012Date of Patent: April 16, 2013Assignee: National Chiao Tung UniversityInventors: Wei-I Lee, Yen-Hsien Yeh, Yin-Hao Wu, Tzu-Yi Yu
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Publication number: 20120184102Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.Type: ApplicationFiled: May 18, 2011Publication date: July 19, 2012Applicant: National Chiao Tung UniversityInventors: Wei-I Lee, Kuei-Ming Chen, Yin-Hao Wu, Yen-Hsien Yeh
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Publication number: 20120052691Abstract: The invention discloses a treating method to produce various patterns on the surface by using gases with ability to etch the group III nitride semiconductor in certain conditions. The selective etching makes some specific patterns on group III nitride semiconductor surface, and different forms of the patterns can be controlled by the selective etching conditions.Type: ApplicationFiled: March 16, 2011Publication date: March 1, 2012Applicant: National Chiao Tung UniversityInventors: Wei-I Lee, Ying-Chia Hsu, Yen-Hsien Yeh, Kuei-Ming Chen
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Publication number: 20110316001Abstract: A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved.Type: ApplicationFiled: September 7, 2011Publication date: December 29, 2011Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Wei I Lee, Hsin Hsiung Huang, Kuei Ming Chen, Yen Hsien Yeh
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Patent number: 7893931Abstract: A shift register array includes a plurality of first shift registers, a second shift register, a first connection line, a second connection line, and a third connection line. A signal output terminal of each first shift register overlaps the first connection line and the third connection line without electric connection. The first connection line is connected to a signal input terminal of the second shift register. The second connection line is connected to a signal output terminal of the second shift register, and establishes a plurality of electric connection paths. When one of the first shift registers malfunctions, the corresponding connection points and overlapping points are cut or connected so that the malfunctioned first shift register can be replaced by the second shift register.Type: GrantFiled: August 9, 2007Date of Patent: February 22, 2011Assignee: Au Optronics Corp.Inventors: Chun-Chin Wei, Yen-Hsien Yeh, Shih Hsun Lo
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Publication number: 20100252834Abstract: A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved.Type: ApplicationFiled: October 5, 2009Publication date: October 7, 2010Applicant: National Chiao Tung UniversityInventors: Wei I LEE, Hsin Hsiung Huang, Kuei Ming Chen, Yen Hsien Yeh
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Patent number: 7627077Abstract: A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.Type: GrantFiled: May 16, 2008Date of Patent: December 1, 2009Assignee: Au Optronics Corp.Inventors: Chun-ching Wei, Shih-hsun Lo, Yen-hsien Yeh, Chen-lun Chiu, Yang-en Wu
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Publication number: 20080285705Abstract: A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.Type: ApplicationFiled: May 16, 2008Publication date: November 20, 2008Applicant: AU OPTRONICS CORP.Inventors: Chun-ching Wei, Shih-hsun Lo, Yen-hsien Yeh, Chen-lun Chiu, Yang-en Wu
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Publication number: 20080055505Abstract: A control circuit equipped with electrostatic discharge (ESD) protection includes a plurality of shift registers, a plurality of buses coupled to the plurality of shift registers, a common line, a set of ESD protection components coupled to a set of the plurality of the buses for protecting the plurality of buses from ESD events; and a set of current paths coupled between the set of the ESD protection components and the common line for providing the ESD current paths to pass through.Type: ApplicationFiled: June 21, 2007Publication date: March 6, 2008Inventors: Yen-Hsien Yeh, Chun-Ching Wei, Shih-Hsun Lo
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Publication number: 20080043006Abstract: A shift register array includes a plurality of first shift registers, a second shift register, a first connection line, a second connection line, and a third connection line. A signal output terminal of each first shift register overlaps the first connection line and the third connection line without electric connection. The first connection line is connected to a signal input terminal of the second shift register. The second connection line is connected to a signal output terminal of the second shift register, and establishes a plurality of electric connection paths. When one of the first shift registers malfunctions, the corresponding connection points and overlapping points are cut or connected so that the malfunctioned first shift register can be replaced by the second shift register.Type: ApplicationFiled: August 9, 2007Publication date: February 21, 2008Applicant: AU OPTRONICS CORP.Inventors: Chun-Chin Wei, Yen-Hsien Yeh, Shih Hsun Lo