Patents by Inventor Yen-Hsin Lai

Yen-Hsin Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210247986
    Abstract: A boot circuit is configured to be coupled to a first memory. Boot information is stored in the first memory. The boot circuit is configured to receive the boot information. The boot circuit includes a first control circuit, a digital signal processing circuit, a detector circuit, a second control circuit, and a memory access circuit. The detector circuit is configured to generate a detection result according to the received boot information. The second control circuit is configured to control the first control circuit according to the detection result, to adjust a transmission parameter for transmitting the boot information. Based on the adjusted transmission parameter, the boot information is retransmitted from the first memory, via the memory access circuit, to the digital signal processing circuit. The digital signal processing circuit performs a boot process according to the retransmitted boot information.
    Type: Application
    Filed: January 27, 2021
    Publication date: August 12, 2021
    Inventor: Yen-Hsin LAI
  • Patent number: 9666279
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Grant
    Filed: June 26, 2016
    Date of Patent: May 30, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 9640259
    Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 2, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
  • Patent number: 9633729
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: April 25, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Publication number: 20160307629
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Application
    Filed: June 26, 2016
    Publication date: October 20, 2016
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 9425204
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: August 23, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Publication number: 20160079251
    Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 17, 2016
    Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
  • Publication number: 20160035421
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Application
    Filed: October 7, 2015
    Publication date: February 4, 2016
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 9236453
    Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
    Type: Grant
    Filed: March 30, 2014
    Date of Patent: January 12, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
  • Publication number: 20150091073
    Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.
    Type: Application
    Filed: March 30, 2014
    Publication date: April 2, 2015
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
  • Publication number: 20150092498
    Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
    Type: Application
    Filed: May 6, 2014
    Publication date: April 2, 2015
    Applicant: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
  • Patent number: 8456916
    Abstract: An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.
    Type: Grant
    Filed: July 4, 2012
    Date of Patent: June 4, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang
  • Patent number: 8363475
    Abstract: A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: January 29, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang
  • Publication number: 20120273860
    Abstract: An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.
    Type: Application
    Filed: July 4, 2012
    Publication date: November 1, 2012
    Applicant: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang
  • Patent number: 8199578
    Abstract: A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: June 12, 2012
    Assignee: eMemory Technology Inc.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Ching-Sung Yang
  • Publication number: 20110299336
    Abstract: A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 8, 2011
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Ching-Sung Yang
  • Publication number: 20110242893
    Abstract: A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.
    Type: Application
    Filed: March 30, 2010
    Publication date: October 6, 2011
    Applicant: EMEMORY TECHNOLOGY INC.
    Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang