Patents by Inventor Yen-Hsin Lai
Yen-Hsin Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968512Abstract: In an example, a speaker device may include a first transducer and a second transducer. The first transducer may include a first diaphragm, a first magnetic circuit, and a first voice coil disposed in a magnetic gap of the first magnetic circuit to cause vibration of the first diaphragm. The second transducer may include a second diaphragm, a second magnet circuit, and a second voice coil disposed in a magnetic gap of the second magnetic circuit to cause vibration of the second diaphragm. Further, the speaker device may include a magnetic plate having a first surface coupled to the first transducer and a second surface coupled to the second transducer. The first surface is opposite to the second surface.Type: GrantFiled: June 22, 2022Date of Patent: April 23, 2024Assignee: Hewlett-Packard Development Company, L.P.Inventors: Yen-Hsin Ho, Yi-Ying Lai, Chen-Hui Hu, Chen-Yu Chang
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Publication number: 20240071956Abstract: Semiconductor structures and methods for forming the same are provided. A method according to the present disclosure includes forming active regions on a substrate, forming an interconnect structure over the active regions, the interconnect structure including a plurality of dielectric layers and a guard ring disposed within the dielectric layers, etching an opening through the interconnect structure and at least a first portion of the active regions, the opening extending into the substrate, and forming a via structure within the opening. The via structure is surrounded by the guard ring when viewed along a direction perpendicular to a top surface of the substrate.Type: ApplicationFiled: April 21, 2023Publication date: February 29, 2024Inventors: Chih Hsin YANG, Yen Lian LAI, Dian-Hau CHEN, Mao-Nan WANG
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Publication number: 20210247986Abstract: A boot circuit is configured to be coupled to a first memory. Boot information is stored in the first memory. The boot circuit is configured to receive the boot information. The boot circuit includes a first control circuit, a digital signal processing circuit, a detector circuit, a second control circuit, and a memory access circuit. The detector circuit is configured to generate a detection result according to the received boot information. The second control circuit is configured to control the first control circuit according to the detection result, to adjust a transmission parameter for transmitting the boot information. Based on the adjusted transmission parameter, the boot information is retransmitted from the first memory, via the memory access circuit, to the digital signal processing circuit. The digital signal processing circuit performs a boot process according to the retransmitted boot information.Type: ApplicationFiled: January 27, 2021Publication date: August 12, 2021Inventor: Yen-Hsin LAI
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Patent number: 9666279Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.Type: GrantFiled: June 26, 2016Date of Patent: May 30, 2017Assignee: eMemory Technology Inc.Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
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Patent number: 9640259Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.Type: GrantFiled: November 20, 2015Date of Patent: May 2, 2017Assignee: eMemory Technology Inc.Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
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Patent number: 9633729Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.Type: GrantFiled: October 7, 2015Date of Patent: April 25, 2017Assignee: eMemory Technology Inc.Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
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Publication number: 20160307629Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.Type: ApplicationFiled: June 26, 2016Publication date: October 20, 2016Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
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Patent number: 9425204Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.Type: GrantFiled: May 6, 2014Date of Patent: August 23, 2016Assignee: eMemory Technology Inc.Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
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Publication number: 20160079251Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.Type: ApplicationFiled: November 20, 2015Publication date: March 17, 2016Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
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Publication number: 20160035421Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.Type: ApplicationFiled: October 7, 2015Publication date: February 4, 2016Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
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Patent number: 9236453Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.Type: GrantFiled: March 30, 2014Date of Patent: January 12, 2016Assignee: eMemory Technology Inc.Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
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Publication number: 20150092498Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.Type: ApplicationFiled: May 6, 2014Publication date: April 2, 2015Applicant: eMemory Technology Inc.Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
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Publication number: 20150091073Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.Type: ApplicationFiled: March 30, 2014Publication date: April 2, 2015Applicant: EMEMORY TECHNOLOGY INC.Inventors: Yi-Hung Li, Yen-Hsin Lai, Ming-Shan Lo, Shih-Chan Huang
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Patent number: 8456916Abstract: An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.Type: GrantFiled: July 4, 2012Date of Patent: June 4, 2013Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang
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Patent number: 8363475Abstract: A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.Type: GrantFiled: March 30, 2010Date of Patent: January 29, 2013Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang
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Publication number: 20120273860Abstract: An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.Type: ApplicationFiled: July 4, 2012Publication date: November 1, 2012Applicant: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang
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Patent number: 8199578Abstract: A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.Type: GrantFiled: June 3, 2010Date of Patent: June 12, 2012Assignee: eMemory Technology Inc.Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Ching-Sung Yang
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Publication number: 20110299336Abstract: A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory.Type: ApplicationFiled: June 3, 2010Publication date: December 8, 2011Applicant: EMEMORY TECHNOLOGY INC.Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Ching-Sung Yang
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Publication number: 20110242893Abstract: A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Applicant: EMEMORY TECHNOLOGY INC.Inventors: Hsin-Ming Chen, Shih-Chen Wang, Wen-Hao Ching, Yen-Hsin Lai, Hau-Yan Lu, Ching-Sung Yang