Patents by Inventor Yen-Hsin Liu
Yen-Hsin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953839Abstract: In a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an EUV lithography system. One or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. The stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.Type: GrantFiled: December 5, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Yu Tu, Shao-Hua Wang, Yen-Hao Liu, Chueh-Chi Kuo, Li-Jui Chen, Heng-Hsin Liu
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Patent number: 11935747Abstract: A method of manufacturing a semiconductor device includes depositing a photoresist material over a substrate. The substrate is rotated to spread the photoresist material. A gas is blown to an edge of the substrate when rotating the substrate. The rotating of the substrate is stopped. The blowing of the gas is stopped.Type: GrantFiled: June 30, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Hsin Liu, Ming-Jhih Kuo, Chun-Yen Tai
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Patent number: 11862690Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.Type: GrantFiled: April 23, 2021Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Wen Hsiao, Chun-Yen Tai, Yen-Hsin Liu, Ming-Jhih Kuo, Ming-Feng Shieh
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Publication number: 20230005737Abstract: A method of manufacturing a semiconductor device includes depositing a photoresist material over a substrate. The substrate is rotated to spread the photoresist material. A gas is blown to an edge of the substrate when rotating the substrate. The rotating of the substrate is stopped. The blowing of the gas is stopped.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Hsin LIU, Ming-Jhih KUO, Chun-Yen TAI
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Publication number: 20220344478Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: Ming-Wen HSIAO, Chun-Yen TAI, Yen-Hsin LIU, Ming-Jhih KUO, Ming-Feng SHIEH
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Patent number: 9153506Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.Type: GrantFiled: July 6, 2012Date of Patent: October 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien Rhone Wang, Kewei Zuo, Chen-Hua Yu, Jing-Cheng Lin, Yen-Hsin Liu
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Patent number: 8945983Abstract: A method embodiment includes forming a packaging unit by attaching a die to a packaging substrate, applying plasma treatment to a first portion of the packaging substrate, wherein the first portion corresponds to a portion of the packaging substrate underneath the die, not applying plasma treatment to a second portion of the packaging substrate, wherein the second portion of the packaging substrate surrounds the first portion of the packaging substrate, and applying an underfill material over the first portion of the packaging substrate.Type: GrantFiled: March 15, 2013Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Hsin Liu, Cing He Chen, Kewei Zuo, Chien Rhone Wang
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Publication number: 20140183760Abstract: A method embodiment includes forming a packaging unit by attaching a die to a packaging substrate, applying plasma treatment to a first portion of the packaging substrate, wherein the first portion corresponds to a portion of the packaging substrate underneath the die, not applying plasma treatment to a second portion of the packaging substrate, wherein the second portion of the packaging substrate surrounds the first portion of the packaging substrate, and applying an underfill material over the first portion of the packaging substrate.Type: ApplicationFiled: March 15, 2013Publication date: July 3, 2014Inventors: Yen-Hsin Liu, Cing He Chen, Kewei Zuo, Chien Rhone Wang
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Publication number: 20140011301Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.Type: ApplicationFiled: July 6, 2012Publication date: January 9, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien Rhone Wang, Kewei Zuo, Chen-Hua Yu, Jing-Cheng Lin, Yen-Hsin Liu
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Publication number: 20130067142Abstract: A method of judging problem storage regions adapted for a flash memory storage device includes steps of: sending a writing order to a flash memory chip for writing a written data to an appointed storage paging; when the flash memory chip beginning writing the written data to the appointed storage paging, getting the first time; when the flash memory chip finishing writing the written data to the appointed storage paging, getting the second time; calculating a writing time according to the first time and the second time; if the writing time not coincident with a standard value, then labeling the appointed storage paging as a problem storage region and copying the written data to a backup paging; updating a Mapping Table.Type: ApplicationFiled: March 21, 2012Publication date: March 14, 2013Applicant: A-DATA TECHNOLOGY (SUZHOU) CO.,LTD.Inventors: Young-Joon Choi, Kuo-Chung Liao, Yen-Hsin Liu, Chiang-Chang Hsien, Yun-Hui Wang, Chih-Ming Hsu
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Patent number: 7317632Abstract: A non-volatile memory storage device with functions of boosting supply voltage and signal level can adopt a non-volatile memory having an operating voltage higher than the supply voltage provided by the host device as a storage medium. The non-volatile memory storage device includes a supply voltage booster, a non-volatile memory storage unit and a controller. The supply voltage booster boosts the lower supply voltage provided by the host device up to the higher operating voltage of the non-volatile memory. The controller adjusts the interface signal to a proper interface signal level by cooperating with the supply voltage and the operating voltage so as to avoid the interface from damage owing to an over high signal level or avoid the non-volatile memory unit from not correctly receiving signal due to an over low signal level.Type: GrantFiled: January 30, 2006Date of Patent: January 8, 2008Assignee: A-Data Technology Co., Ltd.Inventors: Li-Pai Chen, Ming-Dar Chen, Hsiang-An Hsieh, Yen-Hsin Liu
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Publication number: 20070220254Abstract: A secure digital memory device comprising a first memory chip, a second memory chip, and a controller. The controller is coupled to the first and second memory chips and operates in an automatic backup mode of the secure digital memory device. In the automatic backup mode, the controller configures the first and second memory chips as main and backup memory partitions respectively. When data is written into the secure digital memory device, the controller writes the data to the main memory partition and into the backup memory partition to serve as backup data.Type: ApplicationFiled: August 1, 2006Publication date: September 20, 2007Inventor: Yen-Hsin Liu
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Publication number: 20070133299Abstract: A non-volatile memory storage device with functions of boosting supply voltage and signal level can adopt a non-volatile memory having an operating voltage higher than the supply voltage provided by the host device as a storage medium. The non-volatile memory storage device includes a supply voltage booster, a non-volatile memory storage unit and a controller. The supply voltage booster boosts the lower supply voltage provided by the host device up to the higher operating voltage of the non-volatile memory. The controller adjusts the interface signal to a proper interface signal level by cooperating with the supply voltage and the operating voltage so as to avoid the interface from damage owing to an over high signal level or avoid the non-volatile memory unit from not correctly receiving signal due to an over low signal level.Type: ApplicationFiled: January 30, 2006Publication date: June 14, 2007Inventors: Li-Pai Chen, Ming-Dar Chen, Hsiang-An Hsieh, Yen-Hsin Liu