Abstract: A comparator circuit having an offset voltage includes a first input circuit, a second input circuit and a control circuit. The first input circuit includes a first input terminal receiving a first input signal. The second input circuit includes a second input terminal receiving a second input signal. The control circuit is coupled to a first intermediate terminal and a second intermediate terminal and resets a voltage at the first intermediate terminal and a voltage at the second intermediate terminal according to an offset cancellation voltage. The first intermediate terminal is coupled between the first input terminal and a first output terminal of the comparator circuit, the second intermediate terminal is coupled between the second input terminal and a second output terminal of the comparator circuit, and the first intermediate terminal and the second intermediate terminal are symmetric terminals in the comparator circuit.

Abstract: An analog-to-digital converting system includes at least one first main analog-to-digital converting unit, at least one second main analog-to-digital converting unit, at least one auxiliary analog-to-digital converting unit, and a calibration unit. Each first main analog-to-digital converting unit is located on a first channel. The first channel includes sample period. Each first main analog-to-digital converting unit receives a first sampling value. Each first sampling value includes a first sample clock. An analog-to-digital converting method calibrates timing-skew of the analog-to-digital converters by delaying a time difference on the sampling value.