Patents by Inventor Yen-Hsing Chen

Yen-Hsing Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563088
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 24, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20230020271
    Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.
    Type: Application
    Filed: September 21, 2022
    Publication date: January 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11557666
    Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.
    Type: Grant
    Filed: November 22, 2020
    Date of Patent: January 17, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20220416068
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11508818
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: November 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20220367358
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20220344474
    Abstract: A superlattice structure includes a substrate. A first superlattice stack is disposed on the substrate. The first superlattice stack includes a first superlattice layer, a second superlattice layer and a third superlattice layer disposed from bottom to top. Three stress relaxation layers respectively disposed between the first superlattice layer and the second superlattice layer, the second superlattice layer and the third superlattice layer and on the third superlattice layer. Each of the stress relaxation layers includes a group III-V compound layer. The thickness of each of the stress relaxation layers should be greater than a relaxation critical thickness.
    Type: Application
    Filed: May 31, 2021
    Publication date: October 27, 2022
    Inventors: Yu-Ming Hsu, Chun-Liang Kuo, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20220320292
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Application
    Filed: February 28, 2022
    Publication date: October 6, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20220310794
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 29, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11437319
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20220262942
    Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20220245318
    Abstract: For a method of manufacturing a semiconductor device, a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged relative to first and second perpendicular directions, the layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction. The method includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information.
    Type: Application
    Filed: June 22, 2021
    Publication date: August 4, 2022
    Inventors: Yen-Pin CHEN, Florentin DARTU, Wei-Chih HSIEH, Tzu-Hen LIN, Chung-Hsing WANG
  • Patent number: 11398046
    Abstract: The present invention provides an object position determination circuit including a receiving circuit and a detecting circuit. In operations of the object position determination circuit, the receiving circuit receives an image signal; and the detecting circuit detects a position of an object in an Nth frame of the image signal, determines a partial region within an (N+M)th frame of the image signal according to the position of the object in the Nth frame, and only detects the partial region within the (N+M)th frame to determine a position of the object in the (N+M)th frame, wherein N and M are positive integers.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: July 26, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Teng-Hsiang Yu, Chun-Hsing Hsieh, Yen-Lin Chen
  • Publication number: 20220208694
    Abstract: A semiconductor structure includes a substrate including a device region, a peripheral region surrounding the device region, and a transition region disposed between the device region and the peripheral region. An epitaxial layer is disposed on the device region, the peripheral region, and the transition region. A first portion of the epitaxial layer on the peripheral region has a poly-crystal structure.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 30, 2022
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11355626
    Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 7, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20220093778
    Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.
    Type: Application
    Filed: November 22, 2020
    Publication date: March 24, 2022
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Tsung-Mu Yang, Yu-Ren Wang
  • Patent number: 11257939
    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: February 22, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Yu-Chi Wang, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20220045173
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Application
    Filed: October 21, 2021
    Publication date: February 10, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20210249528
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.
    Type: Application
    Filed: April 8, 2020
    Publication date: August 12, 2021
    Inventors: Yu-Ming Hsu, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20210151591
    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, in which the buffer layer includes a first buffer layer and a second buffer layer. Preferably, the first buffer layer includes a first layer of the first buffer layer comprising AlyGa1-yN on the substrate and a second layer of the first buffer layer comprising AlxGa1-xN on the first layer of the first buffer layer. The second buffer layer includes a first layer of the second buffer layer comprising AlwGa1-wN on the first buffer layer and a second layer of the second buffer layer comprising AlzGa1-zN on the first layer of the second buffer layer, in which x>z>y>w.
    Type: Application
    Filed: December 12, 2019
    Publication date: May 20, 2021
    Inventors: Yen-Hsing Chen, Yu-Ming Hsu, Yu-Chi Wang, Tsung-Mu Yang, Yu-Ren Wang