Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Abstract: The power supply controller is for use in a power supply circuit, for reducing acoustic noise. The power supply control circuit generates a control signal according to a voltage identification (VID) signal and a voltage sense signal, to operate a power switch in a power stage circuit, thus converting an input voltage to an output voltage. The power supply control circuit includes a conversion circuit and a PWM control circuit. The conversion circuit includes a DAC and a slope control circuit. When the power supply controller operates in an acoustic noise reduction mode and when a present level is higher than a requested level, the slope control circuit adjusts a descending slope of an analog voltage identification signal which is generated according to the VID signal, so as to restrain a decrease velocity of the output voltage to be higher than zero but not higher than a predetermined velocity.

Abstract: The power supply controller is for use in a power supply circuit, for reducing acoustic noise. The power supply control circuit generates a control signal according to a voltage identification (VID) signal and a voltage sense signal, to operate a power switch in a power stage circuit, thus converting an input voltage to an output voltage. The power supply control circuit includes a conversion circuit and a PWM control circuit. The conversion circuit includes a DAC and a slope control circuit. When the power supply controller operates in an acoustic noise reduction mode and when a present level is higher than a requested level, the slope control circuit adjusts a descending slope of an analog voltage identification signal which is generated according to the VID signal, so as to restrain a decrease velocity of the output voltage to be higher than zero but not higher than a predetermined velocity.

Abstract: A power managing apparatus, a DC-DC control circuit, and a method for enabling a chip are disclosed. The power managing apparatus has an enable pin and the enable pin is used to couple a first level control circuit. The power managing apparatus includes a second level control circuit and a level detecting circuit. The second level control circuit is coupled to the enable pin. The level detecting circuit is coupled to the enable pin and used to detect a control signal on the enable pin. The control signal is transmitted from the first level control circuit. The control signal has at least three levels according to operations of the first level control circuit and the second level control circuit.

Abstract: A power managing apparatus, a DC-DC control circuit, and a method for enabling a chip are disclosed. The power managing apparatus has an enable pin and the enable pin is used to couple a first level control circuit. The power managing apparatus includes a second level control circuit and a level detecting circuit. The second level control circuit is coupled to the enable pin. The level detecting circuit is coupled to the enable pin and used to detect a control signal on the enable pin. The control signal is transmitted from the first level control circuit. The control signal has at least three levels according to operations of the first level control circuit and the second level control circuit.