Patents by Inventor Yen-Jou Wu
Yen-Jou Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230389309Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Jou WU, Hsin-Hui Lin, Yu-Liang Wang, Chih-Ming Lee, Keng-Ying Liao, Ping-Pang Hsieh, Su-Yu Yeh
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Publication number: 20230253433Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Ying Liao, Yu-Chu Lin, Chih Wei Sung, Shih Sian Wang, Chi-Chung Jen, Yu-chien Ku, Yen-Jou Wu, Huai-jen Tung, Po-Zen Chen
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Patent number: 11652127Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.Type: GrantFiled: April 17, 2020Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S. S. Wang
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Publication number: 20230062401Abstract: A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Ken-Ying LIAO, Chih-Wei SUNG, Tzu-Pin LIN, Huai-jen TUNG, Po-Zen CHEN, Yen-Jou WU, Yung-Lung YANG
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Patent number: 11527543Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.Type: GrantFiled: June 30, 2020Date of Patent: December 13, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Jou Wu, Chih-Ming Lee, Keng-Ying Liao, Ping-Pang Hsieh, Su-Yu Yeh, Hsin-Hui Lin, Yu-Liang Wang
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Publication number: 20220367495Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Jou WU, Chih-Ming LEE, Keng-Ying LIAO, Ping-Pang Hsieh, Su-Yu YEH, Hsin-Hui LIN, Yu-Liang WANG
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Publication number: 20220367559Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-Zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-Kai Tsao, Yung-Lung Yang
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Patent number: 11502123Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.Type: GrantFiled: April 17, 2020Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-kai Tsao, Yung-Lung Yang
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Publication number: 20220359606Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S.S. Wang
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Publication number: 20220359781Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
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Patent number: 11430909Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.Type: GrantFiled: May 4, 2020Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
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Publication number: 20210327945Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S.S. Wang
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Publication number: 20210327951Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-Zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-Kai Tsao, Y.L. Yang
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Publication number: 20210036179Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.Type: ApplicationFiled: May 4, 2020Publication date: February 4, 2021Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su