Abstract: A method includes following steps. A first gate dielectric layer is deposited over a first semiconductor channel and a second semiconductor channel. A second gate dielectric layer is deposited over the first gate dielectric layer. A layer is formed over the second gate dielectric layer using atomic layer deposition (ALD) cycles each comprising sequentially performing a first pulse step for a first pulse time, a first purge step for a first purge time, a second pulse step for a second pulse time, and a second purge step for a second purge time. A ratio of the first purge time to the first pulse time is greater than a ratio of the second purge time to the second pulse time. The layer is patterned to expose a portion of the second gate dielectric layer. The exposed portion of the second gate dielectric layer is etched.

Abstract: A method comprises forming first and second fins each comprising alternately stacking first and second semiconductor layers; forming dummy gate structures over the first and second fins, and gate spacers on either side of the dummy gate structures; removing the dummy gate structures to form first and second gate trenches; removing the first semiconductor layers such that the second semiconductor layers are suspended in the first and second gate trenches; depositing a first dielectric layer around the second semiconductor layers and a second dielectric layer around the first dielectric layer; performing an ALD process to form a hard mask layer around the second dielectric layer, the ALD process comprising pulsing a first precursor for a first pulse time longer than about one second; patterning the hard mask layer; and etching a portion of the second gate dielectric layer in the second gate trench.

Abstract: A method comprises forming first and second fins each comprising alternately stacking first and second semiconductor layers; forming dummy gate structures over the first and second fins, and gate spacers on either side of the dummy gate structures; removing the dummy gate structures to form first and second gate trenches; removing the first semiconductor layers such that the second semiconductor layers are suspended in the first and second gate trenches; depositing a first dielectric layer around the second semiconductor layers and a second dielectric layer around the first dielectric layer; performing an ALD process to form a hard mask layer around the second dielectric layer, the ALD process comprising pulsing a first precursor for a first pulse time longer than about one second; patterning the hard mask layer; and etching a portion of the second gate dielectric layer in the second gate trench.