Patents by Inventor Yen-Jun Huang

Yen-Jun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038855
    Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate having a source/drain feature and a gate structure formed thereon; forming an interlayer dielectric layer on the semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the trench; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling a dielectric material layer in the recess.
    Type: Application
    Filed: April 11, 2023
    Publication date: February 1, 2024
    Inventors: Chung-Hao CAI, Chao-Hsun WANG, Chia-Hsien YAO, Wang-Jung HSUEH, Yen-Jun HUANG, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20240038593
    Abstract: A method includes forming first and second fins disposed on a substrate, forming a gate structure over the first and second fins, epitaxially growing a first source/drain (S/D) feature on the first fin and a second S/D feature on the second fin, depositing a dielectric layer covering the first and second S/D features, etching the dielectric layer to form a trench exposing the first and second S/D features, forming a metal structure in the trench and extending from the first S/D feature to the second S/D feature, performing a cut metal process to form an opening dividing the metal structure into a first segment over the first S/D feature and a second segment over the second S/D feature, and depositing an isolation feature in the opening. The isolation feature separates the first segment from the second segment.
    Type: Application
    Filed: June 13, 2023
    Publication date: February 1, 2024
    Inventors: Chung-Hao Cai, Chia-Hsien Yao, Yen-Jun Huang, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11646346
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming an insulating layer over a semiconductor substrate including a conductive feature, forming an insulating layer with a trench over the semiconductor substrate to expose the conductive feature, and forming a sacrificial liner layer over two opposite sidewalls and a bottom of the trench. Ions are implanted into the conductive feature covered by the sacrificial liner layer, so that a doping region is formed in the conductive feature and has two opposite side edges respectively separated from the two opposite sidewalls of the trench. The sacrificial liner layer is removed after forming the doping region, and a conductive connecting structure is formed in the trench. The two opposite sidewalls of the conductive connecting structure are respectively separated from the two corresponding opposite sidewalls of the trench by an air spacer.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Cai, Chun-Po Chang, Chien-Yuan Chen, Yen-Jun Huang, Ting Fang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20220328622
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming an insulating layer over a semiconductor substrate including a conductive feature, forming an insulating layer with a trench over the semiconductor substrate to expose the conductive feature, and forming a sacrificial liner layer over two opposite sidewalls and a bottom of the trench. Ions are implanted into the conductive feature covered by the sacrificial liner layer, so that a doping region is formed in the conductive feature and has two opposite side edges respectively separated from the two opposite sidewalls of the trench. The sacrificial liner layer is removed after forming the doping region, and a conductive connecting structure is formed in the trench. The two opposite sidewalls of the conductive connecting structure are respectively separated from the two corresponding opposite sidewalls of the trench by an air spacer.
    Type: Application
    Filed: April 8, 2021
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao CAI, Chun-Po CHANG, Chien-Yuan CHEN, Yen-Jun HUANG, Ting FANG, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20220223743
    Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first fin structure and a second fin structure over a substrate, a first source/drain feature disposed over the first fin structure and a second source/drain feature disposed over the second fin structure, a dielectric feature disposed over the first source/drain feature, and a contact structure formed over the first source/drain feature and the second source/drain feature. The contact structure is electrically coupled to the second source/drain feature and is separated from the first source/drain feature by the dielectric feature.
    Type: Application
    Filed: October 15, 2021
    Publication date: July 14, 2022
    Inventors: Chung-Hao Cai, Yen-Jun Huang, Ting Fang, Chia-Hsien Yao, Cheng-Ming Lee, Fu-Kai Yang, Mei-Yun Wang