Patents by Inventor Yen-Li Huang

Yen-Li Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395559
    Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 12112953
    Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
  • Publication number: 20240332393
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, LTD.
    Inventors: Hsu-Kai CHANG, Jhih-Rong HUANG, Yen-Tien TUNG, Chia-Hung CHU, Shuen-Shin LIANG, Tzer-Min SHEN, Pinyen LIN, Sung-Li WANG
  • Publication number: 20240293536
    Abstract: The present invention relates to a porcine bivalent subunit vaccine composition in a single dose. The porcine bivalent subunit vaccine composition includes porcine bivalent antigen, CpG adjuvant and a dual phase adjuvant. The porcine bivalent antigen consists of a classical swine fever virus (CSFV)-E2 recombinant protein and a porcine circovirus type 2 (PCV2)-ORF2 recombinant protein, both of which are produced by a mammalian cell expression system. The porcine bivalent subunit vaccine composition in a single dose can confer effectively immune protection against CSFV and PCV2 via a single vaccination without boost vaccination.
    Type: Application
    Filed: December 22, 2023
    Publication date: September 5, 2024
    Applicant: National Pingtung University Of Science And Technology
    Inventors: Hso-Chi Chaung, Wen-Bin Chung, Yen-Li Huang, Chi-Chih Chen, Yu-Chieh Chen
  • Patent number: 12040372
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: July 16, 2024
    Assignee: Tawian Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu, Shuen-Shin Liang, Tzer-Min Shen, Pinyen Lin, Sung-Li Wang