Abstract: A method includes forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region; forming a first top-tier transistor over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second top-tier transistor over the second bottom-tier transistor, the second top-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second top-tier transistors sharing a same source/drain region, wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is different than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.

Abstract: A memory cell includes a first and second transmission pass-gate, a read word line and a write word line. The first transmission pass-gate includes a first and second pass-gate transistor. The second transmission pass-gate includes a third and fourth pass-gate transistor. The read word line is on a first metal layer above a front-side of a substrate. The write word line is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate. The first pass-gate transistor and the third pass-gate transistor are turned on in response to the write word line signal during a write operation. The second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the read word line signal during the write operation after the first pass-gate transistor and the third pass-gate transistor are turned on.

Abstract: An integrated circuit device includes a first transistor having a first-type channel and a second transistor having a second-type channel at a front side of a substrate. The first transistor is stacked over the second transistor. The integrated circuit device also includes a power line connected to a source terminal of the first transistor. The first transistor has a gate terminal configured to receive a control signal and has a drain terminal connected to both a gate terminal and a drain terminal of the second transistor. The integrated circuit device further includes a memory power line connected to a source terminal of the second transistor and a memory circuit configured to receive a supply voltage from the memory power line.

Abstract: An integrated circuit (IC) device includes a plurality of memory segments. Each memory segment includes a plurality of memory cells, and a local bit line electrically coupled to the plurality of memory cells and arranged on a first side of the IC device. The IC device further includes a global bit line electrically coupled to the plurality of memory segments, and arranged on a second side of the IC device. The second side is opposite the first side in a thickness direction of the IC device.

Abstract: A memory cell array includes a first bank of memory cells, a second bank of memory cells adjacent to the first bank of memory cells, a first set of bit lines and a second set of bit lines. The first set of bit lines extend in a first direction, is coupled to the first bank of memory cells, and is on at least a first metal layer above a front-side of a substrate. The second set of bit lines extend in the first direction, is coupled to the second bank of memory cells, and is on at least a second metal layer below a back-side of the substrate opposite from the front-side of the substrate.

Abstract: A static random access memory (SRAM) includes: first and second CFET stacks, each of which includes a first active region (AR), e.g., N-type, stacked in a first direction on a second AR (e.g., P-type), each CFET stack representing a complementary FET (CFET) architecture; an upper half of a third CFET stack; a lower half of a fourth CFET stack; the first and second CFET stacks including FETs that comprise a latch of the SRAM; the first CFET stack further including FETs that comprise first and third ports of the SRAM; the second CFET stack further including FETs that comprise second and fourth ports of the SRAM; the lower half of the fourth CFET stack including FETs that comprise a fifth port of the SRAM; and the upper half of the third CFET stack including FETs that comprise a sixth port of the SRAM.

Abstract: A dual-port memory cell includes a first, second, third, and fourth pass-gate transistor, and a first and a second word line. The first pass-gate transistor includes a first gate on a first level. The second pass-gate transistor includes a second gate on a second level below the first level. The third pass-gate transistor includes a third gate on the first level. The fourth pass-gate transistor includes a fourth gate on the second level. The first word line is on a first metal layer above a front-side of a substrate, and is coupled to the first and third pass-gate transistors that correspond to a first port of the dual-port memory cell. The second word line is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth pass-gate transistors that correspond to a second port of the dual-port memory cell.

Abstract: A memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first and second word line. The first inverter is coupled to the first and third transistor. The second inverter is coupled to the first inverter and the first and third transistor. The first word line is configured to supply a first word line signal, is on a first metal layer above a front-side of a substrate, and is coupled to the first and third transistor. The second word line is configured to supply a second word line signal, and is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and is coupled to the second and fourth transistor. At least the first, second, third or fourth transistor are on the front-side of the substrate.

Abstract: A memory macro includes an input/output (I/O) circuit positioned in a semiconductor wafer, a column of memory cells including first and second subsets of contiguous memory cells extending away from the I/O circuit in the semiconductor wafer, wherein the first subset is positioned between the I/O circuit and the second subset, a first bit line coupled to the I/O circuit and extending on one of a frontside or a backside of the semiconductor wafer along the first subset and terminating at the second subset, and a second bit line coupled to the I/O circuit and extending on the other of the frontside or the backside along the first and second subsets. Each memory cell of the first subset is electrically connected to the first bit line, and each memory cell of the second subset is electrically connected to the second bit line.

Abstract: An integrated circuit (IC) device includes a memory array including a plurality of memory cells, a first word line over the memory array and electrically coupled to at least one first memory cell among the plurality of memory cells, and a second word line under the memory array and electrically coupled to at least one second memory cell among the plurality of memory cells. Each memory cell among the plurality of memory cells includes complementary field-effect transistor (CFET) devices.