Abstract: The present disclosure provides a scalable power distribution system including a power distribution device, the power distribution includes a plurality of input modules and a plurality of output modules. The input module includes a connector for receiving the input power. The output module has a plurality of output ports. The output module receives the input power of the connector of the corresponding input module, or receives the input power of the connector of the input module neighboring to the corresponding input module. The input module receives the plural types of input power, and the power distribution system selectively receives one or more times of the input power through one or more of the plurality of input modules to provide one or more times of the output power to one or more of the plurality of output ports.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: A method is provided that includes forming a first metal layer of a seal structure over a micro-electromechanical system (MEMS) structure and over a channel formed through the MEMS structure to an integrated circuit of a semiconductor structure. The first metal layer is formed at a first temperature. The method includes forming a second metal layer over the first metal layer. The second metal layer is formed at a second temperature less than the first temperature. The method includes performing a first cooling process to cool the semiconductor structure.

Abstract: A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.

Abstract: One or more semiconductor processing tools may deposit a contact etch stop layer on a substrate. In some implementations, the contact etch stop layer is comprised of less than approximately 12 percent hydrogen. Depositing the contact etch stop layer may include depositing contact etch stop layer material at a temperature of greater than approximately 600 degrees Celsius, at a pressure of greater than approximately 150 torr, and/or with a ratio of at least approximately 70:1 of NH3 and SiH4, among other examples. The one or more semiconductor processing tools may deposit a silicon-based layer above the contact etch stop layer. The one or more semiconductor processing tools may perform an etching operation into the silicon-based layer until reaching the contact etch stop layer to form a trench isolation structure.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.

Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.

Abstract: A method for monitoring a shock wave in an extreme ultraviolet light source includes irradiating a target droplet in the extreme ultraviolet light source apparatus of an extreme ultraviolet lithography tool with ionizing radiation to generate a plasma and to detect a shock wave generated by the plasma. One or more operating parameters of the extreme ultraviolet light source is adjusted based on the detected shock wave.

Abstract: The present disclosure discloses a low dropout regulator apparatus having noise-suppression mechanism. An operational amplifier circuit includes a differential input circuit, an amplifying output circuit and a first and a second resistive components. The differential input circuit is coupled between first connection nodes and a ground terminal to receive a reference voltage and a feedback voltage. The amplifying output circuit includes a first and a second transistor pair circuits. The first transistor pair circuit is coupled between a power supply and second connection nodes. The second transistor pair is coupled between the second connection nodes and the ground terminal and has an amplifying output terminal generating an amplified voltage. The first and the second resistive components are coupled between the first and the second connection nodes.

Abstract: A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.

Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Abstract: A backlight module includes the following features. A light guide plate has a viewing angle convergence structure, a light-incident surface and a surface connected to the light-incident surface. The viewing angle convergence structure is located at the surface. The prism plate has first prism columns and second prism columns disposed cross to each other. The inverse prism plate has third prism columns respectively having a first side surface and a second side surface. The first side surface and the second side surface are connected to each other and are respectively connected to the second surface. The first side surface faces a side of the backlight module with the light-emitting element, and the second side surface faces away from the side. An included angle between the first side surface and the second surface is larger than an included angle between the second side surface and the second surface.

Abstract: A backlight module includes the following features. A light guide plate has a viewing angle convergence structure, a light-incident surface and a surface connected to the light-incident surface. The viewing angle convergence structure is located at the surface. The prism plate has first prism columns and second prism columns disposed cross to each other. The inverse prism plate has third prism columns respectively having a first side surface and a second side surface. The first side surface and the second side surface are connected to each other and are respectively connected to the second surface. The first side surface faces a side of the backlight module with the light-emitting element, and the second side surface faces away from the side. An included angle between the first side surface and the second surface is larger than an included angle between the second side surface and the second surface.

Abstract: A switchable backlight module is disclosed. The switchable backlight module includes two light source modules arranged parallelly with respect to a plane. Each of the light source modules includes a turning film and a LGP. The LGP is of an edge-lit type arranged parallelly under the turning film. A light ray enters the LGP from a light incident side of the LGP, exits the LGP from a light emergent surface of the LGP, enters the turning film, and exits the turning film from a surface of the turning film away from the LGP. The light incident side of the LGP of one of the light source modules is perpendicular to the light incident side of the LGP of the other light source module. The switchable backlight module is in an anti-peeping mode having a narrow viewing angle when only an upper one of the light source modules emits light.

Abstract: A front light module includes a reflective display device, a front light guide, and a light emitting unit plate. The front light guide plate includes a micro-structure. The micro-structure has a first angle between a surface thereof close to the light emitting unit and an upper surface of the front light guide plate. The micro-structure has a second angle between a surface thereof away from the light emitting unit and the upper surface of the front light guide plate. The micro-structure has a third angle between the surface thereof close to the light emitting unit and the surface thereof away from the light emitting unit. The first angle is within a range between 30 degrees and 60 degrees, the second angle is within a range between 30 degrees and 59 degrees, and the third angle is greater than 90 degrees.

Abstract: A front light module includes a reflective display device, a front light guide, and a light emitting unit plate. The front light guide plate includes a micro-structure. The micro-structure has a first angle between a surface thereof close to the light emitting unit and an upper surface of the front light guide plate. The micro-structure has a second angle between a surface thereof away from the light emitting unit and the upper surface of the front light guide plate. The micro-structure has a third angle between the surface thereof close to the light emitting unit and the surface thereof away from the light emitting unit. The first angle is within a range between 30 degrees and 60 degrees, the second angle is within a range between 30 degrees and 59 degrees, and the third angle is greater than 90 degrees.

Abstract: A backlight module includes a light guide plate and a light source module. The light guide plate includes a light receiving surface, a light exit surface, and a bottom surface. The light exit surface is connected to a first end of the light receiving surface. The bottom surface is connected to a second end of the light receiving surface opposite to the first end and located opposite to the light exit surface. The bottom surface includes a central region and a peripheral girdle region at least partially surrounding the central region. The central region includes a plurality of first reflecting structures, and the peripheral girdle region includes a plurality of second reflecting structures. The second reflecting structure is different from the first reflecting structure. The light source module is disposed along the light receiving surface and provides light beams incident into the light receiving surface.