Patents by Inventor Yen-Lung Chiu

Yen-Lung Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240126001
    Abstract: A switchable backlight module is disclosed. The switchable backlight module includes two light source modules arranged parallelly with respect to a plane. Each of the light source modules includes a turning film and a LGP. The LGP is of an edge-lit type arranged parallelly under the turning film. A light ray enters the LGP from a light incident side of the LGP, exits the LGP from a light emergent surface of the LGP, enters the turning film, and exits the turning film from a surface of the turning film away from the LGP. The light incident side of the LGP of one of the light source modules is perpendicular to the light incident side of the LGP of the other light source module. The switchable backlight module is in an anti-peeping mode having a narrow viewing angle when only an upper one of the light source modules emits light.
    Type: Application
    Filed: July 19, 2023
    Publication date: April 18, 2024
    Inventors: YU-HUAN CHIU, CHIEN-WEI LIAO, YEN-LUNG CHEN
  • Patent number: 8230302
    Abstract: A data protection method is provided. The data protection method is adapted for a plurality of pages of a plurality of blocks in a memory. The data protection method records bit error weight values and erasing times of the blocks during routine operations of the memory. Therefore, when the system is in an idle status, the data of those blocks having higher bit error weight values can be recovered. Further, the data protection method moves data of those blocks having less erasing times to other blocks, so as to release the blocks having less erasing times from the data area for use. Then, the data protection method utilizes all blocks of the non-volatile memory in an average manner, so as to effectively protect the data saved in the memory and average the erasing operations.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: July 24, 2012
    Assignee: ALi Corporation
    Inventors: Wei-Tsz Hung, Yen-Lung Chiu, Yu-Hsiang Chiu
  • Publication number: 20100122114
    Abstract: A data protection method is provided. The data protection method is adapted for a plurality of pages of a plurality of blocks in a memory. The data protection method records bit error weight values and erasing times of the blocks during routine operations of the memory. Therefore, when the system is in an idle status, the data of those blocks having higher bit error weight values can be recovered. Further, the data protection method moves data of those blocks having less erasing times to other blocks, so as to release the blocks having less erasing times from the data area for use. Then, the data protection method utilizes all blocks of the non-volatile memory in an average manner, so as to effectively protect the data saved in the memory and average the erasing operations.
    Type: Application
    Filed: February 5, 2009
    Publication date: May 13, 2010
    Applicant: ALI CORPORATION
    Inventors: Wei-Tsz Hung, Yen-Lung Chiu, Yu-Hsiang Chiu
  • Publication number: 20090276680
    Abstract: An error correction method is applicable for accessing a data in a storage medium. The method includes the steps of: encoding a portion of the data and the whole data to produce a partial data parity for that portion of the data and a whole data parity for the whole data; using the partial data parity to decode the corresponding portion of the data and the corresponding partial data parity in order to correct error bits from the corresponding portion of the data and from the partial data parity according to the decoded result; using the whole data parity to decode the whole data and the whole data parity in order to correct the error bit from the whole data and the whole data parity according to the decoded result; and outputting the corrected data.
    Type: Application
    Filed: January 12, 2009
    Publication date: November 5, 2009
    Inventor: Yen-Lung CHIU
  • Patent number: 5739059
    Abstract: The present invention is a method of manufacturing a high/low resistance on a mix-mode product. The method includes forming a polysilicon layer over a wafer. A blanket ion implantation is performed to implant ions into the entire polysilicon layer. The polysilicon layer is then separated into a high resistance area and a low resistance area. The low resistance area top surface is raised higher than the high resistance area. A photoresist is then formed on the polysilicon areas. The photoresist is subsequently etched back to the top surface of the low resistance areas. A second implant is done on the low resistance area.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: April 14, 1998
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Pai Chen, Yen-Lung Chiu