Abstract: A communications system that pseudo-randomly dithers the widths of chips that are multiplied by bit symbols for spread spectrum purposes. The system includes a first random sequence generator that generates a first sequence of random numbers at a sample rate and a decision processor responsive to the first sequence of random numbers that generates a separate command at the sample rate each time one of the random numbers exceeds a predetermined threshold. The system further includes a second random sequence generator that generates select random numbers, where the second random number generator changes the select random number each time it receives one of the commands. The system also includes a chip width processor responsive to the random numbers from the second random sequence generator, where the chip width processor selects a new set of chips each having a certain width in response to receiving each random number.

Abstract: A communications system including a transmitter having a modulator that converts information bits to samples, a transmitter pseudo random number generator that generates a sequence of transmitter random numbers defining a time dilation function, and a transmitter time varying delay processor responsive to the samples and the time dilation function, where the transmitter time varying delay processor dithers the samples in time based on the time dilation function. The system also includes a receiver responsive to the dithered samples from the transmitter, where the receiver includes a receiver pseudo random number generator that generates a sequence of receiver random numbers in sync with the transmitter random numbers, a receiver time varying delay processor responsive to the receiver random numbers and the dithered samples, where the receiver time varying delay processor removes the dithering of the samples, and a demodulator for demodulating the samples to recover the information bits.

Abstract: A sub-sampling system that is part of a modulator in a transmitter employing a chaos based architecture and including a symbol mapper and a chaos generator. The system includes M-number of channels each receiving a sequence of chaos samples from the generator and a delay device in all of the channels except one that delay the chaos samples at different delay times. The system also includes a sub-sampler in all of the channels that receive the delayed samples, where each sub-sampler outputs every predetermined one of the chaos samples and a register in each channel each storing a predetermined number of the sub-sampled chaos samples. A selection switch responsive to the stored sub-sampled chaos samples from the registers, where the selection switch is responsive to a selection signal from the symbol mapper that selects one of the registers to output the sequences of stored sub-sampled chaos samples from the system.