Patents by Inventor Yen-Miao LIN

Yen-Miao LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10872831
    Abstract: A method of forming a semiconductor package includes dispensing an adhesive on a substrate that has an integrated circuit die attached thereon, placing a lid over the integrated circuit die such that a bottom surface of the lid caps at least a portion of the adhesive, and pressing the lid against the substrate such that a portion of the adhesive is squeezed from a space between the bottom surface of the lid and the substrate onto a sidewall of the lid.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Shin Han, Yen-Miao Lin, Chung-Chih Chen, Hsien-Liang Meng
  • Publication number: 20190252277
    Abstract: A method of forming a semiconductor package includes dispensing an adhesive on a substrate that has an integrated circuit die attached thereon, placing a lid over the integrated circuit die such that a bottom surface of the lid caps at least a portion of the adhesive, and pressing the lid against the substrate such that a portion of the adhesive is squeezed from a space between the bottom surface of the lid and the substrate onto a sidewall of the lid.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Shin HAN, Yen-Miao LIN, Chung-Chih CHEN, Hsien-Liang MENG
  • Patent number: 10269669
    Abstract: A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The lid is disposed over the substrate. The lid includes a cap portion and a foot portion extending from a bottom surface of the cap portion. The cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess. The adhesive includes a sidewall portion and a bottom portion. The sidewall portion contacts a sidewall of the foot portion. The bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Shin Han, Yen-Miao Lin, Chung-Chih Chen, Hsien-Liang Meng
  • Publication number: 20180166351
    Abstract: A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The lid is disposed over the substrate. The lid includes a cap portion and a foot portion extending from a bottom surface of the cap portion. The cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess. The adhesive includes a sidewall portion and a bottom portion. The sidewall portion contacts a sidewall of the foot portion. The bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate.
    Type: Application
    Filed: June 7, 2017
    Publication date: June 14, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Shin HAN, Yen-Miao LIN, Chung-Chih CHEN, Hsien-Liang MENG
  • Publication number: 20130270121
    Abstract: The present invention discloses a method for fabricating a copper nanowire with high density twins, which comprises steps: providing a template having a top surface, a bottom surface and a plurality of through-holes penetrating the top surface and the bottom surface and having a diameter of smaller than 55 nm; placing the template in a copper-containing electrolyte at a low temperature lower than ambient temperature and applying a pulse current to perform an electrodeposition process to form a copper nanowire with twin structures in each through-hole. The pulse current increases the probability of stacking faults in the deposited copper ions. The low temperature operation favors formation of nucleation sites of twins. Therefore, the copper nanowire has higher density of twins. Thereby is effectively inhibited electromigration of the copper nanowire.
    Type: Application
    Filed: February 27, 2013
    Publication date: October 17, 2013
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chien-Neng LIAO, Yu-Lun CHUEH, Tsung-Cheng CHAN, Yen-Miao LIN