Patents by Inventor Yen-Ming Peng

Yen-Ming Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210384350
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Application
    Filed: August 24, 2021
    Publication date: December 9, 2021
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 11107922
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Grant
    Filed: December 29, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 10840376
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Publication number: 20200144422
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Application
    Filed: December 29, 2019
    Publication date: May 7, 2020
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 10326006
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Publication number: 20190165173
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 30, 2019
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Publication number: 20190148523
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Patent number: 10204843
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: February 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Patent number: 10164059
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Patent number: 10164071
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Publication number: 20180337267
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Patent number: 10014251
    Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Grant
    Filed: March 5, 2016
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien
  • Publication number: 20180076109
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.
    Type: Application
    Filed: November 9, 2017
    Publication date: March 15, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei LIN, Yen-Ming PENG, Han-Wei YANG, Chen-Chung LAI
  • Patent number: 9818666
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Publication number: 20170069757
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Application
    Filed: January 12, 2016
    Publication date: March 9, 2017
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Publication number: 20170033030
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 2, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei LIN, Yen-Ming PENG, Han-Wei YANG, Chen-Chung LAI
  • Patent number: 9472508
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Patent number: 9412866
    Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) selectivity stress films that apply a stress that improves the performance of semiconductor devices underlying the BEOL selectivity stress films, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices having a first device type. A stress transfer element is located within a back-end-of-the-line stack at a position over the one or more semiconductor devices. A selectivity stress film is located over the stress transfer element. The selectivity stress film induces a stress upon the stress transfer element, wherein the stress has a compressive or tensile state depending on the first device type of the one or more semiconductor devices. The stress acts upon the one or more semiconductor devices to improve their performance.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gwo-Chyuan Kuoh, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien, Yen-Ming Peng
  • Publication number: 20160190064
    Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Application
    Filed: March 5, 2016
    Publication date: June 30, 2016
    Inventors: Chen-Chung LAI, Kang-Min KUO, Yen-Ming PENG, Gwo-Chyuan KUOH, Han-Wei YANG, Yi-Ruei LIN, Chin-Chia CHANG, Ying-Chieh LIAO, Che-Chia HSU, Bor-Zen TIEN
  • Publication number: 20160118350
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.
    Type: Application
    Filed: January 4, 2016
    Publication date: April 28, 2016
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei LIN, Yen-Ming PENG, Han-Wei YANG, Chen-Chung LAI