Patents by Inventor Yen-Ni Lee

Yen-Ni Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Efficient layout placement of a diode
    Patent number: 9607944
    Abstract: A semiconductor device includes a plurality of first wires and second wires, a first conductive layer, and a second conductive layer. Each of the first wires forms a closed polygon and surrounds a center, and each of the second wires forms the closed polygon and surrounds the center. The first and second wires are interlaced, and none of the first and second wires are coupled to each other. The first conductive layer, having an entire surface structure, is disposed on the first and second wires and coupled to the first wires. The second conductive layer, having an entire surface structure, is disposed on the first and second wires and coupled to the second wires. The first conductive layer is disposed between the second conductive layer and the first and second wires, and the first and second conductive layers are not coupled to each other.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: March 28, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Pei-Heng Hung, Hsiung-Shih Chang, Manoj Kumar, Yen-Ni Lee, Teng-Shao Su