Abstract: A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.

Abstract: A decoder includes a demultiplexer and a number (P) of ADCs, where P?2. The demultiplexer receives a to-be-decoded data signal that is in a PAM-2M format, and demultiplexes the to-be decoded data signal into a number (P) of demultiplexed data signals, where M?2. The ADCs respectively receive the demultiplexed data signals. One of the ADCs is an (M+1)-bit ADC, and converts the corresponding demultiplexed data signal into a digital first decoded signal that contains an M-bits wide data portion and a one-bit wide error portion. Each of the other one(s) of the ADCs is an M-bit ADC, and converts the corresponding demultiplexed data signal into a digital second decoded signal that contains an M-bits wide data portion.

Abstract: A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

Abstract: A receiver includes a channel compensator, a decoder and an adaptive controller. The channel compensator performs channel compensation on an input data signal to generates a feed-in data signal. The decoder demultiplexes a to-be-decoded data signal that originates from the feed-in data signal into multiple demultiplexed data signals, and decoding the demultiplexed data signals respectively into multiple decoded signals. Based on a decoded output that originates from the decoded signals, the adaptive controller performs adaptive calibration on the channel compensator to adjust a gain of the channel compensator with reference to an error portion of a first sample of the decoded signals and a data portion of a second sample of the decoded signals that is generated before the generation of the first sample of the decoded signals.

Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.

Abstract: A decoder includes a demultiplexer and a number (P) of ADCs, where P?2. The demultiplexer receives a to-be-decoded data signal that is in a PAM-2M format, and demultiplexes the to-be decoded data signal into a number (P) of demultiplexed data signals, where M?2. The ADCs respectively receive the demultiplexed data signals. One of the ADCs is an (M+1)-bit ADC, and converts the corresponding demultiplexed data signal into a digital first decoded signal that contains an M-bits wide data portion and a one-bit wide error portion. Each of the other one(s) of the ADCs is an M-bit ADC, and converts the corresponding demultiplexed data signal into a digital second decoded signal that contains an M-bits wide data portion.

Abstract: A plurality of first semiconductor layers and second semiconductor layers are formed over a front side of a substrate. The first semiconductor layers interleave with the second semiconductor layers in a vertical direction. The first semiconductor layers and second semiconductor layers are etched into a plurality of stacks. The etching is performed such that a bottommost first semiconductor layer is etched to have a tapered profile in a cross-sectional view. The bottommost first semiconductor layer is replaced with a dielectric layer. The dielectric layer inherits the tapered profile of the bottommost first semiconductor layer. Gate structures are formed over the stacks. The gate structures each extend in a first horizontal direction. A first interconnect structure is formed over the gate structures. A second interconnect structure is formed over a back side of the substrate.

Abstract: Provided is an anode particulate for a lithium battery, the particulate comprising a polymer foam material having pores and a single or a plurality of primary particles of an anode active material embedded in or in contact with said polymer foam material, wherein said primary particles of anode active material have a total solid volume Va, and said pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.

Abstract: Provided is a method of producing multiple particulates, the method comprising: (a) dispersing multiple primary particles of an anode active material, having a particle size from 2 nm to 20 ?m, and particles of a polymer foam material, having a particle size from 50 nm to 20 ?m, and an optional adhesive or binder in a liquid medium to form a slurry; and (b) shaping the slurry and removing the liquid medium to form the multiple particulates having a diameter from 100 nm to 50 ?m; wherein at least one of the multiple particulates comprises a polymer foam material having pores and a single or a plurality of the primary particles embedded in or in contact with the polymer foam material, wherein the primary particles have a total solid volume Va, and the pores have a total pore volume Vp, and the volume ratio Vp/Va is from 0.1/1.0 to 10/1.

Abstract: In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.

Abstract: A method includes depositing a dummy semiconductor layer and a first semiconductor layer over a substrate, forming spacers on sidewalls of the dummy semiconductor layer, forming a first epitaxial material in the substrate, exposing the dummy semiconductor layer and the first epitaxial material, where exposing the dummy semiconductor layer and the first epitaxial material includes thinning a backside of the substrate, etching the dummy semiconductor layer to expose the first semiconductor layer, where the spacers remain over and in contact with end portions of the first semiconductor layer while etching the dummy semiconductor layer, etching portions of the first semiconductor layer using the spacers as a mask, and replacing a second epitaxial material and the first epitaxial material with a backside via, the backside via being electrically coupled to a source/drain region of a first transistor.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.

Abstract: Provided is anode active material for use in a lithium ion battery, wherein the anode active material is capable of reversibly storing lithium ions therein up to a maximum lithium storage capacity Cmax during a charge or discharge of the battery and the anode active material comprises an amount of solid-electrolyte interphase (SEI) on a surface or in an internal structure of the anode active material wherein the SEI is pre-formed prior to incorporating the anode active material in an anode electrode of the battery. Also provided is a method of producing the pre-formed SEI substances in the anode material; e.g. through repeated lithiation/delithiation procedures.

Abstract: A method for fabricating an integrated circuit structure is provided. The method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately arranged over the semiconductor substrate; patterning the epitaxial stack into a first fin and a second fin, wherein from a top view the first fin extends along a first direction, and the second fin has a first fin line extending along the first direction and a second fin line extending along a second direction different from the first direction; forming a first gate structure over a first portion of the first fin; etching a recess in a second portion of the first fin adjacent the first portion of the first fin; and forming a source/drain feature in the recess.

Abstract: A plurality of first semiconductor layers and second semiconductor layers are formed over a front side of a substrate. The first semiconductor layers interleave with the second semiconductor layers in a vertical direction. The first semiconductor layers and second semiconductor layers are etched into a plurality of stacks. The etching is performed such that a bottommost first semiconductor layer is etched to have a tapered profile in a cross-sectional view. The bottommost first semiconductor layer is replaced with a dielectric layer. The dielectric layer inherits the tapered profile of the bottommost first semiconductor layer. Gate structures are formed over the stacks. The gate structures each extend in a first horizontal direction. A first interconnect structure is formed over the gate structures. A second interconnect structure is formed over a back side of the substrate.

Abstract: A method includes forming a semiconductor substrate, forming hard mask layers (HMs) over the semiconductor substrate, forming first mandrels over the HMs, forming second mandrels along sidewalls of the first mandrels, forming a protective layer over the first mandrels and the second mandrels, removing a portion of the protective layer to expose portions of the first and the second mandrels, removing the exposed portions of the second mandrels with respect to the exposed portions of the first mandrels, removing remaining portions of the protective layer to expose remaining portions of the first and second mandrels, where the exposed portions of the first mandrels and the remaining portions of the first and second mandrels form a mandrel structure, patterning the HMs using the mandrel structure as an etching mask, and patterning the semiconductor substrate to form a fin structure using the patterned HMs as an etching mask.

Abstract: A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.