Patents by Inventor Yen-Pu Chen

Yen-Pu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10747099
    Abstract: The present invention provides a photomask, comprising: a substrate, a first region, a second region and a third region are defined thereon, wherein the third region is disposed between the first region and the second region, a patterned layer disposed on the substrate, wherein the patterned layer comprises a first patterned layer disposed in the first region, a second patterned layer disposed in the second region, and a third patterned layer disposed in the third region, and wherein a thickness of the first patterned layer is equal to a thickness of the second patterned layer, the thickness of the first patterned layer is different from a thickness of the third patterned layer, and at least one recess disposed in the third region.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 18, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Pu Chen, Shu-Yen Liu, Tang-Chun Weng, Tuan-Yen Yu
  • Publication number: 20190361339
    Abstract: The present invention provides a photomask, comprising: a substrate, a first region, a second region and a third region are defined thereon, wherein the third region is disposed between the first region and the second region, a patterned layer disposed on the substrate, wherein the patterned layer comprises a first patterned layer disposed in the first region, a second patterned layer disposed in the second region, and a third patterned layer disposed in the third region, and wherein a thickness of the first patterned layer is equal to a thickness of the second patterned layer, the thickness of the first patterned layer is different from a thickness of the third patterned layer, and at least one recess disposed in the third region.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 28, 2019
    Inventors: Yen-Pu Chen, Shu-Yen Liu, Tang-Chun Weng, Tuan-Yen Yu
  • Patent number: 10395999
    Abstract: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hao Yang, En-Chiuan Liou, Hsiao-Lin Hsu, Tang-Chun Weng, Chia-Ching Lin, Yen-Pu Chen
  • Patent number: 9837282
    Abstract: A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: December 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tang-Chun Weng, Chia-Ching Lin, Yen-Pu Chen, En-Chiuan Liou
  • Patent number: 9761460
    Abstract: A method of fabricating a semiconductor structure is provided and includes the following steps. A semiconductor substrate including fin structures is provided. Each fin structure is partly located in a first region and partly located in a second region adjoining the first region. A fin remove process is performed for removing the fin structures in the second region. A fin cut process with a fin cut mask is performed for cutting a part of the fin structures in the first region. The fin cut mask includes cut patterns and a compensation pattern. The cut patterns are located corresponding to a part of the fin structures in the first region. The compensation pattern is located corresponding to the second region of the semiconductor substrate. A fin bump is formed in the second region and corresponding to the compensation pattern after the fin cut process and the fin remove process.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tang-Chun Weng, Chia-Ching Lin, Yen-Pu Chen, En-Chiuan Liou