Patents by Inventor Yen-Sen Wang
Yen-Sen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967550Abstract: A semiconductor structure and method of forming the same are provided. The semiconductor structure has a conductive structure. The semiconductor structure includes a first conductive line, a second conductive line, a third conductive line and a conductive via. The first conductive line and the second conductive line are located in a first dielectric layer and extend along a first direction. The first conductive line and the second conductive line are spaced from each other by the first dielectric layer therebetween. The third conductive line is located in a second dielectric layer and extends along a second direction. The conductive via is vertically between the first conductive line and the third conductive line, and between the second conductive line and the third conductive line. The conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line.Type: GrantFiled: May 22, 2020Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Wei Chung, Yen-Sen Wang
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Gate-all-around device with different channel semiconductor materials and method of forming the same
Patent number: 11929288Abstract: Semiconductor device and the manufacturing method thereof are disclosed.Type: GrantFiled: November 21, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jhe-Ching Lu, Bao-Ru Young, Yen-Sen Wang, Tsung-Chieh Tsai -
Patent number: 11894263Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.Type: GrantFiled: October 7, 2021Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
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Publication number: 20230386899Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
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Publication number: 20230369313Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Ting-Yun Wu, Yen-Sen Wang, Chung-Yi Lin
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Patent number: 11735579Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.Type: GrantFiled: October 6, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Yun Wu, Yen-Sen Wang, Chung-Yi Lin
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Patent number: 11688654Abstract: Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.Type: GrantFiled: May 27, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Chun Lin, Chung-Yi Lin, Yen-Sen Wang, Bao-Ru Young
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Publication number: 20230116270Abstract: A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.Type: ApplicationFiled: November 7, 2022Publication date: April 13, 2023Inventors: Shu-Wei Chung, Yen-Sen Wang
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Gate-All-Around Device With Different Channel Semiconductor Materials And Method Of Forming The Same
Publication number: 20230078700Abstract: Semiconductor device and the manufacturing method thereof are disclosed.Type: ApplicationFiled: November 21, 2022Publication date: March 16, 2023Inventors: Jhe-Ching Lu, Bao-Ru Young, Yen-Sen Wang, Tsung-Chieh Tsai -
Publication number: 20230035217Abstract: A semiconductor structure includes a substrate; a seal ring region around a circuit region over the substrate, wherein the seal ring region includes a sealing region and a transition region, and wherein the transition region is disposed between the sealing region and the circuit region; and a stack of metal layers disposed over the circuit region, the transition region and the sealing region. A metal layer of the stack of metal layers includes metal seal rings disposed in the sealing region including a first section along a first direction and a second section along a second direction, wherein the second direction is substantially perpendicular to the first direction; and metal transition lines disposed in the transition region along the first section and the second section, wherein the metal transition lines are oriented lengthwise along the first direction.Type: ApplicationFiled: May 5, 2022Publication date: February 2, 2023Inventors: Yen Lian Lai, Chun Yu Chen, Yen-Sen Wang, Chung-Yi Lin
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Publication number: 20230011752Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.Type: ApplicationFiled: October 7, 2021Publication date: January 12, 2023Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
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Publication number: 20220415878Abstract: The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.Type: ApplicationFiled: October 6, 2021Publication date: December 29, 2022Inventors: Ting-Yun Wu, Yen-Sen Wang, Chung-Yi Lin
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Publication number: 20220384279Abstract: Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Inventors: Yen-Chun LIN, Chung-Yi LIN, Yen-Sen WANG, Bao-Ru YOUNG
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Gate-all-around device with different channel semiconductor materials and method of forming the same
Patent number: 11508624Abstract: Semiconductor device and the manufacturing method thereof are disclosed.Type: GrantFiled: July 24, 2020Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jhe-Ching Lu, Bao-Ru Young, Yen-Sen Wang, Tsung-Chieh Tsai -
Patent number: 11508631Abstract: A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.Type: GrantFiled: September 10, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Chun Lin, Bao-Ru Young, Ting-Yun Wu, Yen-Sen Wang, Hsiao-Wen Hsu
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Patent number: 11503711Abstract: An integrated circuit (IC) device according to the present disclosure includes a substrate including a first surface and a second surface opposing the first surface, a redistribution layer disposed over the first surface and including a conductive feature, a passivation structure disposed over the redistribution layer, a metal-insulator-metal (MIM) capacitor embedded in the passivation structure, a dummy MIM feature embedded in the passivation structure and including an opening, a top contact pad over the passivation structure, a contact via extending between the conductive feature and the top contact pad, and a through via extending through the passivation structure and the substrate. The dummy MIM feature is spaced away from the MIM capacitor and the through via extends through the opening of the dummy MIM feature without contacting the dummy MIM feature.Type: GrantFiled: July 27, 2020Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Wei Chung, Yen-Sen Wang
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Publication number: 20220357949Abstract: An integrated circuit (IC) device according to the present disclosure includes a substrate including a first surface and a second surface opposing the first surface, a redistribution layer disposed over the first surface and including a conductive feature, a passivation structure disposed over the redistribution layer, a metal-insulator-metal (MIM) capacitor embedded in the passivation structure, a dummy MIM feature embedded in the passivation structure and including an opening, a top contact pad over the passivation structure, a contact via extending between the conductive feature and the top contact pad, and a through via extending through the passivation structure and the substrate. The dummy MIM feature is spaced away from the MIM capacitor and the through via extends through the opening of the dummy MIM feature without contacting the dummy MIM feature.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Shu-Wei Chung, Yen-Sen Wang
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Patent number: 11495558Abstract: A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.Type: GrantFiled: November 23, 2020Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Wei Chung, Yen-Sen Wang
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Publication number: 20220277128Abstract: Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes receiving an integrated circuit layout, inserting, into the integrated circuit layout, a design containing a first set of Front-End Of Line (FEOL) shapes of an integrated circuit and a first set of Back-End Of Line (BEOL) shapes of the integrated circuit, inserting, into the integrated circuit layout, a set of cells containing a second set of FEOL shapes of the integrated circuit and a second set of BEOL shapes of the integrated circuit, removing a subset of the second set of BEOL shapes that conflict with the design, and providing the integrated circuit layout that includes the design and the set of cells for fabrication of the integrated circuit. The second set of FEOL shapes includes contact shapes that define contacts of the integrated circuit.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Inventors: Yu-Cheng Yeh, Yen-Sen Wang, Ming-Yi Lin
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Patent number: 11334703Abstract: Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes initializing a layout for fabricating an integrated circuit. A plurality of fill cells is inserted into the layout. The plurality of fill cells includes a plurality of fill line shapes that correspond to conductive lines of the integrated circuit. Thereafter, a design is inserted into the layout that includes a plurality of functional shapes. A conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflict with the plurality functional shapes are removed. The layout that includes the plurality of fill cells and the design is provided for fabricating the integrated circuit.Type: GrantFiled: June 29, 2017Date of Patent: May 17, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Cheng Yeh, Yen-Sen Wang, Ming-Yi Lin