Patents by Inventor Yen-Sheng Chang

Yen-Sheng Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963348
    Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
  • Patent number: 7287199
    Abstract: A method capable of detecting a status of a basic input/output system (BIOS) for setting a clock is applied to a clock generating device of a computer motherboard and sets the clock according to a signal status of the BIOS or a trigger signal. A device capable of detecting the BIOS status for setting the clock is also proposed. The device has a crystal oscillator, a frequency control unit, a phase-lock-loop (PLL) spread-spectrum unit electrically connected with the crystal oscillator and the frequency control unit, a memory unit having a clock setting value stored therein, a detection control unit electrically connected with the memory unit and used to detect a signal status, and a logic control unit electrically connected with the PLL spread-spectrum unit, the frequency control unit and the detection control unit.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: October 23, 2007
    Assignee: Giga-Byte Technology Co., Ltd.
    Inventor: Yen Sheng Chang
  • Patent number: 7254759
    Abstract: A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a second FBM. The first and second FBMs are compared, thereby generating a third FBM according to comparison results.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: August 7, 2007
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Tong-Yu Liu, Yen-Sheng Chang
  • Publication number: 20060143550
    Abstract: A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a second FBM. The first and second FBMs are compared, thereby generating a third FBM according to comparison results.
    Type: Application
    Filed: August 15, 2005
    Publication date: June 29, 2006
    Inventors: Tong-Yu Liu, Yen-Sheng Chang