Abstract: A method of fabricating a semiconductor device includes providing a substrate that includes a handle substrate, a bottom cladding layer, and a semiconductor layer stacked in sequence from bottom to top. The substrate includes an electronic integrated circuit (EIC) region and a photonic integrated circuit (PIC) region. A thermal oxidation process is performed on the semiconductor layer in the PIC region to form an oxide layer. A first thickness of the semiconductor layer in the EIC region is greater than a second thickness of the semiconductor layer below the oxide layer. The oxide layer is removed and a PIC structure is formed on the bottom cladding layer in the PIC region. An EIC structure is formed on the bottom cladding layer in the EIC region. An interconnect structure is formed to be electrically connected to the PIC and EIC structures.

Abstract: A silicon photonic platform includes a composite substrate with a first photonic platform layer which includes a photonic platform material. A first signal layer covers the first photonic platform layer, has a top surface, and includes the photonic platform material and a first signal material. A photonic platform spectral signal is different from the first signal material spectral signal. The second photonic platform layer has a top surface, covers at least a portion of the top surface of the first signal, and includes the photonic platform material. The second photonic platform layer includes at least one ridge structure, and forms a silicon photonic platform together with the first photonic platform layer.

Abstract: A photonic integrated circuit structure includes a semiconductor substrate. A waveguide is disposed above the semiconductor substrate and has an inclined plane. A mirror coating layer is conformally disposed on the inclined plane. A cladding layer covers the waveguide and the mirror coating layer. A hole is disposed in the semiconductor substrate or the cladding layer, and the hole overlaps the inclined plane in a vertical direction. In addition, an optical fiber is disposed in the hole to receive a reflected light from the mirror coating layer.

Abstract: A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.

Abstract: A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.

Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.

Abstract: A continuous-time delta-sigma modulator (CT-DSM) includes a loop filter, a pipelined successive-approximation register analog-to-digital converter (SAR ADC), a feedback circuit, an excess loop delay (ELD) compensation circuit, and a logic circuit. The loop filter generates a first intermediate signal according to an input signal, a feedback signal, and a compensation signal. The pipelined SAR ADC generates a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal. The feedback circuit generates the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal. The ELD compensation circuit generates the compensation signal according to at least one output signal of the feedback circuit. The logic circuit generates an output digital code according to the first digital code and the second digital code.

Abstract: Provided is an herbal composition including an extract from an herbal raw material including at least one of Artemisia argyi, Ohwia caudata, Anisomeles indica (L.) O. Ktze, Ophiopogon japonicus, Houttuynia cordata, Platycodon grandiflorus, Glycyrrhiza uralensis, Perilla frutescens, and chrysanthemum. Also provided is a method for preparing the herbal composition and a method for preventing or treating a viral infection by administering an effective amount of the herbal composition to a subject in need thereof.

Abstract: Methods for preparing a void-free protective coating are disclosed herein. The void-free protective coating is used on a dielectric window having a central hole, which is used in a plasma treatment tool. A first protective coating layer is applied to the window, leaving an uncoated annular retreat area around the central hole. The first protective coating layer is polished to produce a flat surface and fill in any voids on the window. A second protective coating layer is then applied upon the flat surface of the first protective coating layer to obtain the void-free coating. This increases process uptime and service lifetime of the dielectric window and the plasma treatment tool.

Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.

Abstract: Methods for preparing a void-free protective coating are disclosed herein. The void-free protective coating is used on a dielectric window having a central hole, which is used in a plasma treatment tool. A first protective coating layer is applied to the window, leaving an uncoated annular retreat area around the central hole. The first protective coating layer is polished to produce a flat surface and fill in any voids on the window. A second protective coating layer is then applied upon the flat surface of the first protective coating layer to obtain the void-free coating. This increases process uptime and service lifetime of the dielectric window and the plasma treatment tool.

Abstract: A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.

Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.

Abstract: A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.

Abstract: A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.

Abstract: Methods for preparing a void-free protective coating are disclosed herein. The void-free protective coating is used on a dielectric window having a central hole, which is used in a plasma treatment tool. A first protective coating layer is applied to the window, leaving an uncoated annular retreat area around the central hole. The first protective coating layer is polished to produce a flat surface and fill in any voids on the window. A second protective coating layer is then applied upon the flat surface of the first protective coating layer to obtain the void-free coating. This increases process uptime and service lifetime of the dielectric window and the plasma treatment tool.

Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.

Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

Abstract: A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.

Abstract: A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.