Abstract: An embodiment of this invention provides a chip scale sensing chip package module, comprising a chip scale sensing chip package, having a sensing chip with a first top substrate and a first bottom substrate opposite to the first top substrate, wherein the sensing chip has a sensing device and a plurality of conductive pads adjacent to the first top substrate, and a plurality of conductive structures connected to the conductive pads by a re-distribution layer adjacent to the first bottom surface; a touch plate having a color layer, comprising a base and a spacer formed on the base, wherein the spacer has a cavity with a bottom wall exposing part of the surface of the base and a side wall surrounding the bottom wall; and a first adhesive layer sandwich between the sensing chip and the touch plate to join the first top surface of the sensing chip to the bottom wall of the cavity of the touch plate and surround the sensing chip by the side wall of the cavity; and a print circuit board placed under the chip scale

Abstract: A chip package includes a chip, a dielectric bonding layer, a carrier, and a redistribution layer. The chip has a substrate, a conductive pad, and a protection layer. The dielectric bonding layer is located on the protection layer and between the carrier and the protection layer. The carrier, the dielectric bonding layer, and the protection layer have a communicated through hole configured to expose the conductive pad. The redistribution layer includes a connection portion and a passive component portion. The connection portion is located on the conductive pad, the sidewall of the through hole, and a surface of the carrier facing away from the dielectric bonding layer. The passive component portion is located on the surface of the carrier, and an end of the passive component portion is connected to the connection portion that is on the surface of the carrier.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A second surface of the wafer is adhered to an ultraviolet tape on a frame, and the temporary bonding layer and the carrier are removed. A protection tape is adhered to the first surface of the wafer. An ultraviolet light is used to irradiate the ultraviolet tape. A dicing tape is adhered to the protection tape and the frame, and the ultraviolet tape is removed. A first cutter is used to dice the wafer from the second surface of the wafer, such that plural chips and plural gaps between the chips are formed. A second cutter with a width smaller than the width of the first cutter is used to cut the protection tape along the gaps.

Abstract: A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract: A method for forming a photosensitive module is provided. The method includes providing a sensing device. The sensing device includes a conducting pad located on a substrate. A first opening penetrates the substrate and exposes the conducting pad. A redistribution layer is in the first opening to electrically connect to the conducting pad. A cover plate is located on the substrate and covers the conducting pad. The method also includes removing the cover plate of the sensing device. The method further includes bonding the sensing device to a circuit board after the removal of the cover plate. The redistribution layer in the first opening is exposed and faces the circuit board. In addition, the method includes mounting an optical component corresponding to the sensing device on the circuit board. A photosensitive module formed by the method is also provided.

Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.

Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

Abstract: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

Abstract: An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract: An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic shielding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.

Abstract: Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer.

Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.