Patents by Inventor Yen-Shih Huang
Yen-Shih Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10705639Abstract: An anti-reflective integrated touch display panel includes an anti-reflective structure and touch electrodes. The anti-reflective structure includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a conducting layer disposed on the second insulating layer, a third insulating layer disposed on the second insulating layer, and a fourth insulating layer disposed on the third insulating layer. The first insulating layer includes silicon oxide or silicon nitride, and has a thickness of 0.1 to 2 micrometers. The second insulating layer includes silicon oxide or strontium oxide, and has a thickness of 0.001 to 0.1 micrometer. The conducting layer includes molybdenum, and has a thickness of 0.01 to 0.05 micrometer. The fourth insulating layer includes silicon nitride, and has a thickness of 0.001 to 0.3 micrometer. The touch electrodes are disposed between the third insulating layer and the fourth insulating layer.Type: GrantFiled: January 29, 2019Date of Patent: July 7, 2020Assignee: Au Optronics CorporationInventors: Chun-Cheng Hung, Wen-Jen Li, Yen-Shih Huang, Chia-Ming Chen, Ting-Wei Ko, Chia-Yuan Yeh
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Publication number: 20200057520Abstract: An anti-reflective integrated touch display panel includes an anti-reflective structure and touch electrodes. The anti-reflective structure includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a conducting layer disposed on the second insulating layer, a third insulating layer disposed on the second insulating layer, and a fourth insulating layer disposed on the third insulating layer. The first insulating layer includes silicon oxide or silicon nitride, and has a thickness of 0.1 to 2 micrometers. The second insulating layer includes silicon oxide or strontium oxide, and has a thickness of 0.001 to 0.1 micrometer. The conducting layer includes molybdenum, and has a thickness of 0.01 to 0.05 micrometer. The fourth insulating layer includes silicon nitride, and has a thickness of 0.001 to 0.3 micrometer. The touch electrodes are disposed between the third insulating layer and the fourth insulating layer.Type: ApplicationFiled: January 29, 2019Publication date: February 20, 2020Applicant: Au Optronics CorporationInventors: Chun-Cheng Hung, Wen-Jen Li, Yen-Shih Huang, Chia-Ming Chen, Ting-Wei Ko, Chia-Yuan Yeh
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Patent number: 9842891Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.Type: GrantFiled: July 28, 2017Date of Patent: December 12, 2017Assignee: AU OPTRONICS CORPORATIONInventors: Chi-Yu Yeh, Chen-Ming Hu, Yen-Shih Huang
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Publication number: 20170323933Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.Type: ApplicationFiled: July 28, 2017Publication date: November 9, 2017Inventors: Chi-Yu YEH, Chen-Ming HU, Yen-Shih HUANG
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Patent number: 9755007Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.Type: GrantFiled: June 14, 2016Date of Patent: September 5, 2017Assignee: AU OPTRONICS CORPORATIONInventors: Chi-Yu Yeh, Chen-Ming Hu, Yen-Shih Huang
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Publication number: 20170133447Abstract: A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a source region, a first drain region, and a second drain region. A first portion of the channel region is connected to the source region, a second portion of the channel region is connected to the first drain region, and a third portion of the channel region is connected to the second drain region. The channel width of the second portion is greater than that of the third portion. A capacitive device is connected to the gate of the first transistor. The second transistor includes a source region connected to the second drain region and a drain region connected to the light-emitting element. The third transistor includes a source region connected to the first drain region and a drain region connected to a capacitive device.Type: ApplicationFiled: June 14, 2016Publication date: May 11, 2017Inventors: Chi-Yu YEH, Chen-Ming HU, Yen-Shih HUANG
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Patent number: 9361828Abstract: A pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, an organic light emitting diode, and a capacitor. The second transistor is electrically connected between a first end and a gate end of the first transistor. The third transistor is electrically connected between the first end of the first transistor and a first supply voltage source. The fourth transistor is electrically connected between a second end of the first transistor and a data input end. The fifth transistor is electrically connected to the second end of the first transistor. The organic light emitting diode is electrically connected between the fifth transistor and a second supply voltage source. The capacitor is electrically connected to the gate end of the first transistor.Type: GrantFiled: October 9, 2014Date of Patent: June 7, 2016Assignee: AU OPTRONICS CORPORATIONInventors: Hsuan-Ming Tsai, Yen-Shih Huang
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Publication number: 20150339976Abstract: A pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, an organic light emitting diode, and a capacitor. The second transistor is electrically connected between a first end and a gate end of the first transistor. The third transistor is electrically connected between the first end of the first transistor and a first supply voltage source. The fourth transistor is electrically connected between a second end of the first transistor and a data input end. The fifth transistor is electrically connected to the second end of the first transistor. The organic light emitting diode is electrically connected between the fifth transistor and a second supply voltage source. The capacitor is electrically connected to the gate end of the first transistor.Type: ApplicationFiled: October 9, 2014Publication date: November 26, 2015Inventors: Hsuan-Ming TSAI, Yen-Shih HUANG
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Patent number: 9070897Abstract: A display panel includes a substrate, a TFT device, a patterned dielectric layer, a patterned metal layer and a bridge line. The TFT device is disposed in a display region. The patterned dielectric layer includes an ILD layer disposed over the TFT device, and a sealant stage disposed in a peripheral region. The patterned metal layer includes a signal line disposed on the ILD layer, and a first connecting line and a second connecting line. The first connecting line is disposed in an inner side of the sealant stage facing the display region, and the first connecting line is electrically connected to the signal line. The second connecting line is disposed in an outer side of the sealant stage opposite to the display region. The bridge line is disposed under the sealant stage, and the first connecting line and the second connecting line are electrically connected through the bridge line.Type: GrantFiled: May 15, 2012Date of Patent: June 30, 2015Assignee: AU Optronics Corp.Inventors: Yen-Shih Huang, Chia-Yuan Yeh, Bo-Feng Lee, Ta-Wei Chiu
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Patent number: 8928046Abstract: A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure.Type: GrantFiled: October 13, 2010Date of Patent: January 6, 2015Assignee: Industrial Technology Research InstituteInventors: Jing-Yi Yan, Chu-Yin Hung, Hsiao-Chiang Yao, Yen-Yu Wu, Yen-Shih Huang
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Patent number: 8513670Abstract: A pixel structure and a pixel circuit having multi-display mediums are provided. A storage capacitor and a first display medium are disposed in different layers, so as to overlap the storage capacitor with a pixel electrode of the first display medium. Accordingly, an area of the first display medium can be increased for enlarging an aperture ratio of the pixel. Furthermore, because a third pixel electrode is disposed in a conductive layer, the third pixel electrode can control/drive a second display medium under a substrate.Type: GrantFiled: October 26, 2010Date of Patent: August 20, 2013Assignee: Industrial Technology Research InstituteInventors: Jing-Yi Yan, Yen-Shih Huang, Chen-Wei Lin, Hua-Chi Cheng
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Publication number: 20130044046Abstract: A display panel includes a substrate, a TFT device, a patterned dielectric layer, a patterned metal layer and a bridge line. The TFT device is disposed in a display region. The patterned dielectric layer includes an ILD layer disposed over the TFT device, and a sealant stage disposed in a peripheral region. The patterned metal layer includes a signal line disposed on the ILD layer, and a first connecting line and a second connecting line. The first connecting line is disposed in an inner side of the sealant stage facing the display region, and the first connecting line is electrically connected to the signal line. The second connecting line is disposed in an outer side of the sealant stage opposite to the display region. The bridge line is disposed under the sealant stage, and the first connecting line and the second connecting line are electrically connected through the bridge line.Type: ApplicationFiled: May 15, 2012Publication date: February 21, 2013Inventors: Yen-Shih Huang, Chia-Yuan Yeh, Bo-Feng Lee, Ta-Wei Chiu
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Patent number: 8368088Abstract: A light-emitting device and a method for manufacturing the same are provided. The light-emitting device comprises a substrate, a light-emitting element and a light-electricity-transforming element. The substrate has a first region and a second region which are non-overlapping. The light-emitting element is disposed over the substrate and located in the second region. The light-electricity-transforming element is disposed over the substrate and located in the first region. At least a portion of a side wall of the light-electricity-transforming element corresponds to at least a portion of a side wall of the light-emitting element, so that at least a side light from the light-emitting element is received and transformed into an electricity power by the light-electricity-transforming device.Type: GrantFiled: December 22, 2010Date of Patent: February 5, 2013Assignee: Industrial Technology Research InstituteInventors: Jing-Yi Yan, Jung-Jie Huang, Shu-Tang Yeh, Yen-Shih Huang, Hung-Chien Lin
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Patent number: 8164544Abstract: A pixel array layout includes a substrate, a plurality of scan lines disposed on the substrate, a plurality of data lines disposed on the substrate, a plurality of pixel units disposed on the substrate, and a pre-discharge conductive layer. Each of the pixel units is electrically connected to at least one of the scan lines and one of the data lines correspondingly, and each of the pixel units has a driving circuit and a pixel electrode electrically connected to the driving circuit. The pre-discharge conductive layer is electrically connected to the driving circuit and extends to an area between two adjacent pixel electrodes from an edge of the substrate, and the pre-discharge conductive layer and the pixel electrodes do not overlap.Type: GrantFiled: July 21, 2009Date of Patent: April 24, 2012Assignee: Industrial Technology Research InstituteInventors: Chen-Wei Lin, Yen-Shih Huang
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Publication number: 20120061689Abstract: A light-emitting device and a method for manufacturing the same are provided. The light-emitting device comprises a substrate, a light-emitting element and a light-electricity-transforming element. The substrate has a first region and a second region which are non-overlapping. The light-emitting element is disposed over the substrate and located in the second region. The light-electricity-transforming element is disposed over the substrate and located in the first region. At least a portion of a side wall of the light-electricity-transforming element corresponds to at least a portion of a side wall of the light-emitting element, so that at least a side light from the light-emitting element is received and transformed into an electricity power by the light-electricity-transforming device.Type: ApplicationFiled: December 22, 2010Publication date: March 15, 2012Inventors: Jing-Yi YAN, Jung-Jie Huang, Shu-Tang Yeh, Yen-Shih Huang, Hung-Chien Lin
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Publication number: 20110285610Abstract: A pixel structure and a pixel circuit having multi-display mediums are provided. A storage capacitor and a first display medium are disposed in different layers, so as to overlap the storage capacitor with a pixel electrode of the first display medium. Accordingly, an area of the first display medium can be increased for enlarging an aperture ratio of the pixel. Furthermore, because a third pixel electrode is disposed in a conductive layer, the third pixel electrode can control/drive a second display medium under a substrate.Type: ApplicationFiled: October 26, 2010Publication date: November 24, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jing-Yi Yan, Yen-Shih Huang, Chen-Wei Lin, Hua-Chi Cheng
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Publication number: 20110254061Abstract: A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure.Type: ApplicationFiled: October 13, 2010Publication date: October 20, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jing-Yi Yan, Chu-Yin Hung, Hsiao-Chiang Yao, Yen-Yu Wu, Yen-Shih Huang
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Publication number: 20110115769Abstract: A hybrid image display system and an operating method thereof. The system has an electro-phoretic display (EPD) element, an organic light emitting diode (OLED), a current generating circuit and a switch. The EPD element has a first and a second terminal. The OLED has an anode and a cathode. The current generating circuit has a power terminal, a control terminal and an output terminal, wherein the output terminal is coupled to the anode of the OLED. The switch is controlled by a scan signal. When the switch is turned on, a data signal is transmitted to the first terminal of the EPD element and to the control terminal of the current generating circuit.Type: ApplicationFiled: February 4, 2010Publication date: May 19, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ming-Hua HSIEH, Heng-Lin PAN, Chen-Wei LIN, Yen-Shih HUANG
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Publication number: 20110096061Abstract: A driving method for a LED display panel time-anneals threshold voltage shifting of a driving transistor. The driving transistor has a gate terminal coupled to a data input terminal, a source terminal coupled to a cathode via a LED, and a drain terminal coupled to a system voltage. The method includes inserting a black image after an image frame is displayed. During the time period of inserting the black image, a positive voltage is applied to the cathode to turn off the LED. A negative bias from the gate terminal to the drain terminal is produced to cause voltage level of the gate terminal to be less than the source terminal.Type: ApplicationFiled: September 15, 2010Publication date: April 28, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chen-Wei Lin, Yen-Shih Huang, Ming-Hua Hsieh, Heng-Lin Pan
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Publication number: 20100164931Abstract: A pixel circuit adaptable for a pixel array including a first scan line and a second scan line is provided. An illumination unit is coupled to a first node, including a light emitting diode that illuminates based on a voltage level of the first node. A first circuit is coupled to the first node, the first scan line and a data signal. A second circuit including one or more transistors, is coupled to the first node, the second scan line and a reference voltage. The second scan line has a scan order before that of the first scan line by one or more lines. When the first scan line is activated, the first circuit passes the data signal to the first node. When the second scan line is activated, the second circuit passes the reference voltage to the first node.Type: ApplicationFiled: November 11, 2009Publication date: July 1, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chen Wei Lin, Yen-Shih Huang