Patents by Inventor Yen-Shyh Ho

Yen-Shyh Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5517045
    Abstract: A new method of forming a self-aligned contact is achieved. A pattern of polysilicon gate electrode stack including a silicon oxide gate dielectric, a polysilicon gate electrode, a first thermal polyoxide layer over the top of said polysilicon gate electrode layer, a first silicon nitride layer over said first thermal polyoxide layer, and a TEOS layer over said silicon nitride layer is provided on a silicon substrate. Each of the layers has its side open to the ambient. Inert ions are implanted into the substrate which is not covered by the polysilicon gate electrode stack in such a manner as to reduce the possibility of the oxidation of the surface of the substrate. The pattern of polysilicon gate electrode stack and the surface of the said substrate are subjected to a thermal oxidizing ambient which causes oxidation of the sides open to the ambient of the polysilicon layer to form a second polyoxide layer on the sides of the polysilicon layer.
    Type: Grant
    Filed: November 4, 1994
    Date of Patent: May 14, 1996
    Assignee: Taiwan Semiconductor Manufacturing Co.
    Inventors: Yen-Shyh Ho, Chien-Yung Chen
  • Patent number: 5364804
    Abstract: A method of forming a self-aligned contact is disclosed. A pattern of polysilicon gate electrode stack including a silicon oxide gate dielectric, a polysilicon gate electrode, a first thermal polyoxide layer over the top of said polysilicon gate electrode layer, a first silicon nitride layer over said first thermal polyoxide layer, and a TEOS layer over said silicon nitride layer is provided on a silicon substrate. Each of the layers has its sides open to the ambient. Inert ions are implanted into the substrate which is not covered by the polysilicon gate electrode stack in such a manner as to reduce the possibility of the oxidation of the surface of the substrate. The pattern of polysilicon gate electrode stack and the surface of the said substrate are subjected to a thermal oxidizing ambient which causes oxidation of the sides open to the ambient of the polysilicon layer to form a second polyoxide layer on the sides of the polysilicon layer.
    Type: Grant
    Filed: November 3, 1993
    Date of Patent: November 15, 1994
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yen-Shyh Ho, Chien-Yung Chen