Abstract: A two-stage weighted capacitor network for use as an analog-to-digital or digital-to-analog converter is described. A capacitor ladder is included having two similar groups of capacitors connected in parallel. In each group the parallel capacitors have values starting with value C and decreasing in binary fractional amounts C/2.sup.1, C/2.sup.2, C/2.sup.3, C/2.sup.4 etc. to C/2.sup.n-1. The two groups are interconnected through a coupling capacitor of value C/2.sup.n-1 and each of the capacitors in the two groups are selectively connected through switches to either a reference voltage or ground potential. A high gain amplifier connected as an inverting amplifier with a 2C capacitor feedback path is connected to the capacitor ladder.

Abstract: The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to a FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed.