Patents by Inventor Yen-Ta LIN

Yen-Ta LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12243848
    Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hong-Ta Kuo, Yen Hao Huang, I-Shi Wang, Ming-Yi Shen, Tzu-Ping Yang, Hsing-Yu Wang, Huang-Liang Lin, Yin-Tung Chou, Yuan-Hsin Chi, Sheng-Yuan Lin
  • Publication number: 20230387233
    Abstract: In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 30, 2023
    Inventors: Yung-Hsiang CHAN, An-Hung TAI, Hui-Chi CHEN, J.F. CHUEH, Yen-Ta LIN, Ming-Chi HUANG, Cheng-Chieh TU, Jian-Hao CHEN, Kuo-Feng YU
  • Publication number: 20230290824
    Abstract: A method for forming a semiconductor device structure includes forming first nanostructures and second nanostructures over a substrate. The method also includes forming a first metal gate layer surrounding the first nanostructures and over the first nanostructures and the second nanostructures. The method also includes etching back the first metal gate layer over the first nanostructures and the second nanostructures. The method also includes removing the first metal gate layer over the second nanostructures. The method also includes forming a second metal gate layer surrounding the second nanostructures and over the first nanostructures and the second nanostructures.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yao YANG, Chia-Wei CHEN, Wei-Cheng HSU, Jo-Chun HUNG, Yung-Hsiang CHAN, Hui-Chi CHEN, Yen-Ta LIN, Te-Fu YEH, Yun-Chen WU, Yen-Ju CHEN, Chih-Ming SUN