Abstract: A semiconductor device includes a two-dimensional semiconductor layer formed by a two-dimensional semiconductor material having a first formation energy, a two-dimensional metal conductor layer formed by a two-dimensional metal material and covering a surface of the two-dimensional semiconductor layer, and a metal layer covering a surface of the two-dimensional metal conductor layer. The two-dimensional metal material has a second formation energy smaller than the first formation energy. The two-dimensional metal conductor layer is formed by bonding of cations from the metal layer and anions from the two-dimensional semiconductor layer. As such, the contact resistances between the two-dimensional materials and the metals can be effectively reduced, enabling the application of the two-dimensional materials in semiconductor devices such as field-effect transistors.

Abstract: A method includes following steps. First transistors are formed over a substrate. An interconnect structure is formed over the plurality of first transistors. A dielectric layer is formed over the interconnect structure. 2D semiconductor seeds are formed over the dielectric layer. The 2D semiconductor seeds are annealed. An epitaxy process is performed to laterally grow a plurality of 2D semiconductor films respectively from the plurality of 2D semiconductor seeds. Second transistors are formed on the plurality of 2D semiconductor films.

Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

Abstract: A device comprises a plurality of 2D semiconductor nanostructures, a gate structure, a source region, and a drain region. The plurality of 2D semiconductor nanostructures extend in a first direction above a substrate and arranged in a second direction substantially perpendicular to the first direction. The gate structure surrounds each of the plurality of 2D semiconductor nanostructures. The source region and the drain region are respectively on opposite sides of the gate structure.

Abstract: An IC structure comprises a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

Abstract: A semiconductor structure includes a substrate, a buffer layer, and a two-dimensional layered material. The buffer layer is above the substrate and is formed from one of SiC and a nitride-based material. The two-dimensional layered material is above the buffer material. The construction as such permits formation, e.g., of a channel of a transistor from the two-dimensional layered material.

Abstract: A semiconductor structure includes a substrate, a buffer layer, and a two-dimensional layered material. The buffer layer is above the substrate and is formed from one of SiC and a nitride-based material. The two-dimensional layered material is above the buffer material. The construction as such permits formation, e.g., of a channel of a transistor from the two-dimensional layered material.

Abstract: Disclosed is a semiconductor structure comprising a single crystal substrate, a channel layer formed above the substrate from a transition metal dichalcogenides (TMDC) material, and a single crystal epitaxial buffer layer formed between the substrate and the channel layer, wherein the buffer layer is formed from material having a lattice constant mismatch of less than 5% with the lattice constant of the channel layer material. Also, disclosed is a method of forming a semiconductor structure comprising selecting a substrate formed from a single crystal material, preparing the substrate for template growth, growing a template on the substrate wherein the template is formed from single crystal material, and growing channel material on the template wherein the channel material is formed from a TMDC material and wherein the buffer layer material has a lattice constant mismatch of less than 5% with the lattice constant of the channel layer material.

Abstract: Disclosed is a semiconductor structure comprising a single crystal substrate, a channel layer formed above the substrate from a transition metal dichalcogenides (TMDC) material, and a single crystal epitaxial buffer layer formed between the substrate and the channel layer, wherein the buffer layer is formed from material having a lattice constant mismatch of less than 5% with the lattice constant of the channel layer material. Also, disclosed is a method of forming a semiconductor structure comprising selecting a substrate formed from a single crystal material, preparing the substrate for template growth, growing a template on the substrate wherein the template is formed from single crystal material, and growing channel material on the template wherein the channel material is formed from a TMDC material and wherein the buffer layer material has a lattice constant mismatch of less than 5% with the lattice constant of the channel layer material.

Abstract: The present invention relates to a method for growing a non-polar m-plane epitaxial layer on a single crystal oxide substrate, which comprises the following steps: providing a single crystal oxide with a perovskite structure; using a plane of the single crystal oxide as a substrate; and forming an m-plane epitaxial layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process, wherein the non-polar m-plane epitaxial layer may be GaN, or III-nitrides. The present invention also provides an epitaxial layer having an m-plane obtained according to the aforementioned method.

Abstract: The present invention relates to a method for growing a novel non-polar (13 40) plane epitaxy layer of wurtzite structure, which comprises the following steps: providing a single crystal oxide with perovskite structure; using a plane of the single crystal oxide as a substrate; and forming a non-polar (13 40) plane epitaxy layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process. The present invention also provides an epitaxy layer having non-polar (13 40) plane obtained according to the aforementioned method.

Abstract: The present invention relates to a method for growing a novel non-polar (13 40) plane epitaxy layer of wurtzite structure, which comprises the following steps: providing a single crystal oxide with perovskite structure; using a plane of the single crystal oxide as a substrate; and forming a non-polar (13 40) plane epitaxy layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process. The present invention also provides an epitaxy layer having non-polar (13 40) plane obtained according to the aforementioned method.

Abstract: The present invention relates to a method for growing a non-polar m-plane epitaxial layer on a single crystal oxide substrate, which comprises the following steps: providing a single crystal oxide with a perovskite structure; using a plane of the single crystal oxide as a substrate; and forming an m-plane epitaxial layer of wurtzite semiconductors on the plane of the single crystal oxide by a vapor deposition process. The present invention also provides an epitaxial layer having an m-plane obtained according to the aforementioned method.