Abstract: A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

Abstract: Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.

Abstract: A method of processing substrates, in one example microelectronic workpieces, is disclosed that includes forming a multi-layer metal hard mask (MHM) layer in which at least one lower layer of the multi-layer MHM is comprised of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed over one or more underlying layers on a substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be etched using, at least in part, the patterned ALD Ru MHM layer as a mask to protect portion of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.

Abstract: Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

Abstract: A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.

Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.

Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

Abstract: A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

Abstract: A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.

Abstract: Stacked structures, process steps, and methods for via and trench formation use a dielectric etch stop layer (ESL) to reduce or eliminate problems, such as process lag and chamfer erosion, that occur during conventional etch processes. A stacked structure is formed that includes a dielectric ESL within a dielectric layer, such as a low-dielectric (low-K) layer, to form a first low-K layer below the dielectric ESL and a second low-K dielectric layer above the dielectric ESL. When the stacked structure is subsequently etched to form trenches as well as vias through the stacked structure to underlying layers, the dielectric ESL reduces or eliminates RIE lag by ensuring that trenches (regardless of width) stop on the dielectric ESL. The dielectric ESL also acts as a protective layer to protect corners from chamfer erosion during via and trench etch processes.

Abstract: Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

Abstract: Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.

Abstract: An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.

Abstract: Embodiments are disclosed for a method to process microelectronic workpieces including forming a metal hard mask layer including ruthenium (Ru MHM layer) over one or more underlying layers on a substrate for a microelectronic workpiece, etching the Ru MHM layer to provide a patterned Ru MHM layer, and etching the one or more underlying layers using the patterned Ru MHM layer as a mask to protect portion of the one or more underlying layers. For one embodiment, the Ru MHM layer is a material including 95 percent or more of ruthenium (Ru). For another embodiment, the Ru MHM layer is a material including 70 percent or more of ruthenium (Ru). Further, the Ru MHM layer preferably has a selectivity of 10 or greater with respect to a next underlying layer adjacent to the Ru MHM layer, such as a SiN hard mask layer.

Abstract: A method of processing substrates, in one example microelectronic workpieces, is disclosed that includes forming a multi-layer metal hard mask (MHM) layer in which at least one lower layer of the multi-layer MHM is comprised of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed over one or more underlying layers on a substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be etched using, at least in part, the patterned ALD Ru MHM layer as a mask to protect portion of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

Abstract: An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.