Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

Abstract: A method for using an intercom to implement an intelligent calling process, an intelligent calling apparatus and a system is presented. The method is adapted to a site that adopts intercoms to perform a calling process. The system utilizes a server for receiving a calling signal generated by an intelligent calling apparatus. The calling signal records ID information used to represent a calling location. The server obtains the calling location by querying a database. The software process running in the server combines voice signals according to the calling location. A calling voice is generated and sent to the intercoms carried by the personnel member. When any personnel members receive the calling voice by the intercom, this calling process can be completed as the personnel member arrives at the calling location.

Abstract: The disclosure is related to a method for intelligent calling service, an apparatus and a system thereof. The method is performed in a server. When the server receives a service request signal recording a device ID generated by an apparatus for intelligent calling service, call information of service personnel can be obtained based on a service location corresponding to the device ID by querying a database of the server. After that, the server issues a service call signal to service communication devices carried by the service personnel. When a distance between the service communication device and the apparatus for intelligent calling service reaches a threshold, it shows that one of the service personnel is in service. This calling service procedure is done when the server receives a dismissing signal generated by the apparatus or the service communication device near the apparatus.

Abstract: The disclosure is related to an IoT service system with a Bluetooth Low Energy mesh network, and a communication method thereof. The IoT service system includes multiple intelligent service calling devices, multiple service communication devices and an agent node forming a BLE mesh network. One service calling device generates a service request signal that is broadcasted over a BLE mesh network. When a server receives the service request signal through the agent node, a service personnel and his portable service communication device are obtained by querying a database according to identification information relating to the service calling device that generates the service request signal. A service calling signal is therefore formed and broadcasted over the BLE mesh network. If a distance between the service communication device and the service calling device reaches a threshold while the service personnel is in service, a service dismissing signal is generated.

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A gate structure is formed on a semiconductor substrate. The gate structure includes a floating gate electrode, a control gate electrode, a first oxide layer, and a second oxide layer. The control gate electrode is disposed on the floating gate electrode. The first oxide layer is disposed between the floating gate electrode and the semiconductor substrate. The second oxide layer is disposed between the floating gate electrode and the control gate electrode. An oxide spacer layer is conformally on the gate structure and the semiconductor substrate. A nitride spacer is formed on the oxide spacer layer and on a sidewall of the gate structure. An oxidation process is performed after the step of forming the nitride spacer. A thickness of an edge portion of the first oxide layer is increased by the oxidation process.

Abstract: A walkie-talkie messaging system includes a processing controller device, a sensing signal transmission unit, a master walkie-talkie, and a plurality of slave walkie-talkies. The sensing signal transmission unit is connected to the processing controller device via a wired or wireless connection, the processing controller device is connected to the master walkie-talkie via a wired connection, and the master walkie-talkie is connected to the slave walkie-talkies via a wireless connection. The processing controller device further includes a comparison module, a database, a determination module and a schedule module. The database is connected to the comparison module and the determination module, and the determination module is connected to the schedule module. The master walkie-talkie is connected to the processing controller device via an audio line, such that the processing controller device is capable of determining whether the master walkie-talkie is occupied by an activity.

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A gate structure is formed on a semiconductor substrate. The gate structure includes a floating gate electrode, a control gate electrode, a first oxide layer, and a second oxide layer. The control gate electrode is disposed on the floating gate electrode. The first oxide layer is disposed between the floating gate electrode and the semiconductor substrate. The second oxide layer is disposed between the floating gate electrode and the control gate electrode. An oxide spacer layer is conformally on the gate structure and the semiconductor substrate. A nitride spacer is formed on the oxide spacer layer and on a sidewall of the gate structure. An oxidation process is performed after the step of forming the nitride spacer. A thickness of an edge portion of the first oxide layer is increased by the oxidation process.

Abstract: A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

Abstract: A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.

Abstract: An operating method of a memory device includes providing the memory device and performing an erase operation. The memory device includes a substrate, a gate dielectric layer formed on the substrate, a gate conductive layer formed on the gate dielectric layer, a charge trapping layer, a charge blocking layer, a source region, and a drain region. The charge trapping layer has a vertical portion formed on a sidewall of the gate conductive layer and a horizontal portion formed between the substrate and the gate conductive layer. The charge blocking layer is formed between the substrate and the charge trapping layer. The source and drain regions are formed in the substrate and located at two sides of the gate conductive layer respectively. Performing the erase operation includes applying an erase voltage to the gate conductive layer for inducing a BBHH injection and a FN hole tunneling.

Abstract: A method for forming a memory cell structure includes following steps. A substrate including at least a memory cell region defined thereon is provided, and a first gate stack is formed in the memory cell region. A first LDD implantation is performed to form a first LDD at one side of the first gate stack in the memory cell region, and the first LDD includes a first conductivity type. A second LDD implantation is performed to form a second LDD at one side of the first gate stack opposite to the first LDD in the memory cell region, and the second LDD includes the first conductivity type. The first LDD and the second LDD are different from each other.