Patents by Inventor Yen-Ting Tsai

Yen-Ting Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240389343
    Abstract: A method for forming a semiconductor structure includes following operations. A substrate is received. The substrate includes a first dielectric layer and a conducive layer formed in the first dielectric layer. A ferroelectric layer is formed over the first dielectric layer and the conductive layer. A metal oxide semiconductor layer is formed over the ferroelectric layer. An SUT treatment is performed. A temperature of the SUT treatment is less than approximately 400° C.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: MIN-KUN DAI, YEN-CHIEH HUANG, KUO-CHANG CHIANG, HAN-TING TSAI, TSANN LIN, CHUNG-TE LIN
  • Publication number: 20240379870
    Abstract: The problem of providing transistors that can be manufactured to any specified threshold voltage withing a broad range of threshold voltages without creating leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that dipoles form around the interface of the two dielectrics. The dipoles create an electric field that causes a shift in the threshold voltage. The buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is proximate the channel.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 14, 2024
    Inventors: Wu-Wei Tsai, Hai-Ching Chen, Po-Ting Lin, Yan-Yi Chen, Yu-Ming Lin, Chung-Te Lin, Tzer-Min Shen, Yen-Tien Tung
  • Publication number: 20240363671
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Cheng-Hsien Chou, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai
  • Publication number: 20240302575
    Abstract: A manufacturing method for optical lens devices includes: providing a first scratch-resistant layer on a first outer surface of a first protective layer having a structural reinforcement function to form a first reinforced protective layer; providing a second scratch-resistant layer on a second outer surface of a second protective layer having a structural reinforcement function to form a second reinforced protective layer; forming a containing space layer between a first inner surface of the first protective layer and a second inner surface of the second protective layer; providing an intermediate layer in the containing space layer; the first scratch-resistant layer and the first protective layer commonly protecting a first side of the containing space layer while the second scratch-resistant layer and the second protective layer commonly protecting a second side of the containing space layer.
    Type: Application
    Filed: June 20, 2023
    Publication date: September 12, 2024
    Inventors: YUE-CHANG TSAI, TIEN-SHU WU, YEN-TING WU
  • Patent number: 12087801
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Chou, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai
  • Patent number: 12077419
    Abstract: A method and a system for controlling a handling machine, and a non-volatile computer readable recording medium are provided. The method includes: analyzing image data to obtain contour data corresponding to a target in the image data; analyzing the contour data to obtain feature data, where the feature data reflects the position of the target in the physical space; and generating control data based on the feature data, where the control data is adapted to control the handling machine to transport the target in response to the position of the target in the physical space.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: September 3, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Tsung-Ting Tsai, Carlos Andres Betancourt Baca, Yen-Chung Chang, Ching-Yi Liu
  • Patent number: 12078607
    Abstract: A method of characterizing a wide-bandgap semiconductor material is provided. A substrate is provided, which includes a layer stack of a conductive material layer, a dielectric material layer, and a wide-bandgap semiconductor material layer. A mercury probe is disposed on a top surface of the wide-bandgap semiconductor material layer. Alternating-current (AC) capacitance of the layer stack is determined as a function of a variable direct-current (DC) bias voltage across the conductive material layer and the wide-bandgap semiconductor material layer. A material property of the wide-bandgap semiconductor material layer is extracted from a profile of the AC capacitance as a function of the DC bias voltage.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Yu Chang, Ken-Ichi Goto, Yen-Chieh Huang, Min-Kun Dai, Han-Ting Tsai, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12073520
    Abstract: An augmented reality implementing method applied to a server, which includes a plurality of augmented reality objects and a plurality of setting records corresponding to the augmented reality objects respectively is provided. Firstly, the server receives an augmented reality request from a mobile device, where the augmented reality request is related to a target device. Then, the server is communicated with the target device to access current information. Then, the server determines the current information corresponds to which one of the setting records, and selects one of the augmented reality objects based on the determined setting record as a virtual object provided to the mobile device.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: August 27, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Kuo-Chung Chiu, Hsuan-Wu Wei, Yen-Ting Liu, Shang-Chih Liang, Shih-Hua Ma, Yi-Hsuan Tsai, Jun-Ting Chen, Kuan-Ling Chen
  • Publication number: 20240251566
    Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.
    Type: Application
    Filed: April 4, 2024
    Publication date: July 25, 2024
    Inventors: Chung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
  • Patent number: 11704215
    Abstract: A central processing unit includes a core, a state memory, a plurality of bus contacts, a data generation unit, and a bus interface unit. The state memory stores a state, the bus interface unit is coupled to the core and the state memory, and the bus interface unit selectively couples the core to the plurality of bus contacts or the data generation unit according to the state.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: July 18, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Yen-Ting Tsai
  • Publication number: 20220188204
    Abstract: A central processing unit includes a core, a state memory, a plurality of bus contacts, a data generation unit, and a bus interface unit. The state memory stores a state, the bus interface unit is coupled to the core and the state memory, and the bus interface unit selectively couples the core to the plurality of bus contacts or the data generation unit according to the state.
    Type: Application
    Filed: March 18, 2021
    Publication date: June 16, 2022
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: Yen-Ting Tsai
  • Publication number: 20050082562
    Abstract: A nitride light emitting device includes a substrate, a first nitride semiconductor stack formed above the substrate, the first nitride semiconductor stack having an epitaxial surface and a first rough surface, a distance from the epitaxial surface to the substrate being not less than a distance from the rough surface to the substrate, a nitride emitting layer formed on the epitaxial surface, and a second nitride semiconductor stack formed on the nitride emitting layer for promoting the efficiency of capturing light emitted from an LED.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 21, 2005
    Inventors: Chen Ou, Biau-Dar Chen, Shane-Shyan Wey, Yen-Ting Tsai